SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 388

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

3.0
3.1
The ATT20C497 is provided on the board to fully test all of the CRT display modes available
with the SPC8106 including sprite/hardware cursor display.
The ATT20C497 does not support hardware power down mode (only a software sleep mode is
provided). As a result, when the SPC8106 enters hardware power save mode, the ATT20C497
becomes inactive rather than powering down. The RGB outputs will be turned off. The CPU will
not be able to access palette RAM as the /DACRD and /DACWR signals generated by the
SPC8106 will be inactive.
The ATT20C497 has been provided with an external voltage reference.
3.2
This evaluation board supports the 16-bit ISA Bus via standard AT edge connectors. The board
will not work in an 8bit slot. The board will support 8-bit or 16-bit access as configured by MD4.
All standard VGA I/0 addresses are supported. The video BIOS is mapped to the address range
C0000h through C7FFFh.
3.3
512K video memory is installed on the board. A single 256kxl6 DRAM, SMD, SOJ or TSOP
package is used. The DRAM can either have symmetrical or asymmetrical architecture
(selected by MD6).
3.4
The majority of color STN LCD panels require a positive power supply VDDH to provide
between +23V and +40V (Iout=45 mA). For ease of implementation, such a power supply has
been provided as an integral part of this design The VDDH signal can be found on LCD connec-
tor J6 at pin 34. Output voltage is varied by potentiometer R53. To prevent panel damage,
VDDH power supply sequencing is implemented by enabling the VDDH power supply only
when the SPC8106 signal /LCDBIAS is at a low logic level.
3.5
The majority of monochrome STN LCD panels require a negative power supply VLCD to pro-
vide between -18V and -23V (Iout=45 mA). For ease of implementation, such a power supply
has been provided as an integral part of this design. The VLCD signal can be found on LCD
connector J6 at pin 32. Output voltage is varied by potentiometer R55. To prevent panel dam-
age, VLCD power supply sequencing is implemented by enabling the VLCD power supply only
when the SPC8106 signal /LCDBIAS is at a low logic level.
3.6
This evaluation board has provision for testing the SPC8106 hardware power save mode. When
DIP switch SW 1-6 is open, the SPC8106 will operate normally. When SW1-6 is closed, the
SPC8106 will enter hardware power save mode (SUSPEND).
SDU8106B
EV1-12
TECHNICAL DESCRIPTION
ATT20C497 CMOS RAMDAC
ISA Bus Interface
Video Memory
Adjustable LCD Panel Positive Power Supply
Adjustable LCD Panel Negative Power Supply
Hardware Power Save Mode
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
0E
Rev. 1.0 Evaluation Board User Manual
X12-AN-001-01
411-1.0
SPC8106