SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 143

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit7
bit 6
bits 5-0
bits 7-0
bits 1-0
bits 5-4
SPC8106
0D LCD Support Registers 2 RW
XSCL
Enable
0F Secondary Revision Code Register RO
Secondary
Revision
Code Bit 7
10 Extended Function Register 4 RW
n/a
411-1.0
LP Timing
Select
Secondary
Revision
Code Bit 6
n/a
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XSCL Enable
This bit is used to adjust the XSCL shift clock output timing in monochrome mode. When this bit =
0, XSCL is masked off during the horizontal non-display period. When this bit = 1, XSCL is not
masked off during the horizontal non-display period. Refer to “A.C. CHARACTERISTICS” on
page 28 and the LCD panel manufacturer's specification to determine the correct setting of this bit.
This bit does not affect either XSCL or XSCL2 in color panel modes.
LP Timing Select
This bit is used to adjust the LP latch pulse output timing. When this bit = 0, then the LP latch pulse
falling edge occurs 9 clock periods before the falling edge of the shift clock (XSCL). When this bit =
1, then the LP latch pulse falling edge occurs 4 clock periods before the falling edge of the shift
clock. Refer to “A.C. CHARACTERISTICS” on page 28 and the LCD panel manufacturer's specifi-
cation to determine the correct setting of this bit.
WF Count Bits [5:0]
These bits are used to adjust the WF output signal period. The binary value stored in these bits
represents the number of LP pulses - 1 between toggles of the WF output. The power up reset
value of these bits is 20h. A value of 0 programmed in these bits causes the WF output to toggle
every frame. Values of 01h - 3Fh programmed in these bits result in WF toggling every (1 + n) LP
pulses.
Secondary Revision Code Bits [7:0]
The secondary revision code bits are read-only bits that are permanently fixed to the current revi-
sion code of the chip. Note that the primary revision code bits 2-0 in the Primary Revision Code
Register (index 08) are always set to 1 for the SPC8106. For the SPC8106, the Secondary Revi-
sion Code Register contains the value 63h. (The Secondary Revision Code for the SPC8106F0A is
60h and for the SPC8106F0B is 61h.)
DDC2 Monitor Support Bits [1:0]
These two bits read 11b on power-up.
When bit 0 = 1 the MS1 pin is input only; when bit 0 = 0 the MS1 pin is forced low.
When bit 1 = 1 the MS2 pin is input only; when bit 0 = 0 the MS2 pin is forced low.
Monitor ID Bits [2:1]
The Monitor ID Bits allow software to read the status on the monitor sense input pins MS[2:1].
These inputs are not latched and are expected to have external pullup resistors attached, so that if
nothing is connected to them these register bits will read 11.
WF Count
Bit 5
Secondary
Revision
Code Bit 5
Monitor ID
Bit 2
WF Count
Bit 4
Secondary
Revision
Code Bit 4
Monitor ID
Bit 1
X12-SP-001-07
WF Count
Bit 3
Secondary
Revision
Code Bit 3
n/a
WF Count
Bit 2
Secondary
Revision
Code Bit 2
n/a
Hardware Functional Specification
WF Count
Bit 1
Secondary
Revision
Code Bit 1
DDC2
Monitor
Support Bit 1
WF Count
Bit 0
Secondary
Revision
Code Bit 0
DDC2
Monitor
Support Bit 0
SP1-101