SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 79

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

7.7
SPC8106
Symbol
t14
t10
t11
t12
t13
SPC8106 outputs
MA[9:0]
RAS#
LCAS#
UCAS#
DRAM outputs
411-1.0
t1
t2
t3
t4
t5
t6
t7
t8
t9
Note: DRAM access time is guaranteed to be 80 nsec minimum .
MD[15:0]
DRAM Read Cycle Timing - Page Mode
MA[9:0] row address setup to RAS# asserted
MA[9:0] row address hold from RAS# asserted
RAS# precharge
RAS# pulse width
RAS# asserted to LCAS#, UCAS# asserted
MA[9:0] col addr setup to LCAS#, UCAS# asserted (1st)
MA[9:0] col addr hold from LCAS#, UCAS# asserted(1st)
LCAS#, UCAS# asserted to RAS# negated
LCAS#, UCAS# pulse width
MD[15:0] read data setup to LCAS#, UCAS# negated
MD[15:0] read data hold from LCAS#, UCAS# negated
MA[9:0] column address setup to LCAS#, UCAS# asserted
(2 nd - n th page access)
MA[9:0] column address hold from LCAS#, UCAS#
asserted (2 nd - n th page access)
LCAS#, UCAS# precharge
Figure 10 : DRAM Read Cycle Timing - Page
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
t1
t3
row
t2
Table 0-26 DRAM Read Cycle Timing - Page Mode
t5
t6
Parameter
column 1
t9
t10
t7
valid
t11
t14
X12-SP-001-07
t12
column 2
t4
Modesource: 8106_dram_read_pm_01.can
t9
t10
t13
valid
t11
3.5Ts+4
0.5Ts+1
0.5Ts+3
0.5Ts+1
1.5Ts-5
2Ts-10
Ts-14
0.5Ts
Ts-10
Ts-10
0.5Ts
Ts-2
Min
12
0
Hardware Functional Specification
Typ
column n
24.5Ts+13
t8
t9
t10
Max
valid
t11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP1-37