SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 21

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

LCD Panel Interface
SPC8106
Pin Name
YD
LP
XSCL
XSCL2
UD[0:3]
UD[4:7]
LD[0:3]
LD[4:7]
LCDPWR#
WF
411-1.0
Type
O
O
O
O
O
O
O
O
O
O
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Pin #
10
13
12
9
22..25
26..29
16..19
30..33
21
15
Description
Vertical Scanning Start Pulse output. A logic 1 on this signal, sampled by the LCD
module on the falling edge of LP, is used by the panel row drivers (Y drivers) to
indicate the start of the vertical frame.
Latch Pulse output. The falling edge of this signal is used to latch a row of display
data in the LCD module’s column driver shift registers and to turn on the row driver
(Y driver) for that line.
Shift Clock for LCD data. Display data is clocked out of the chip on the rising edge
of this signal, to be shifted into the LCD panel module column drivers (X drivers)
on each falling edge.
This second shift clock is used together with XSCL in 8-bit single color panel mode
to shift in alternate sets of display data. XSCL2 is also used alone as the shift clock
in 8-bit dual color panel mode and 4-bit single color panel mode.
Upper panel display data for dual panel - dual drive mode. For 8-bit single panel-
single drive mode, these bits are the most significant 4-bits of the 8-bit output data
to the panel (data[7:4]). For 4-bit single panel mode, these bits are the 4 bits of
data output to the panel. For 16-bit LCD modes, these outputs are the multiplexed
upper panel data if MD[7]=1 at RESET, or the lower nibble of the upper panel data
if MD[7]=0 at RESET.
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode
upper panel data.
Lower panel display data for dual panel-dual drive mode. For 8-bit single panel-
single drive mode, these bits are the least significant 4 bits of the 8-bit output data
to the panel (data[3:0]). For 4-bit single panel mode, these outputs are driven low.
For 16-bit LCD modes, these outputs are the multiplexed lower panel data if
MD[7]=1 at RESET, or the lower nibble of the lower panel data if MD[7]=0 at
RESET.
When MD[7]=0 at RESET, these pins are the upper nibble of the 16-bit LCD mode
lower panel data.
LCD power control. In normal operation this signal is driven low to enable an
external LCD power supply. This signal is driven high when the chip is put into any
power save mode, when Auxiliary Register 06 bit 0 is set to 1, or when the
Sequencer is in a reset state. It can be used externally to turn off the panel supply
voltage and backlight. After a RESET, this signal is held high until the CRTC is
programmed and running.
LCD Backplane Bias signal. This output toggles once every n LP periods, as
programmed in Auxiliary Register [0D].
Data Sheet
DS-15