upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 293

• Manufacturer Part Number: upd78f0730
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

(10) UF0 EP status 2 register (UF0EPS2)
UF0EPS2
Remark
Bit position
2 to 0
This register indicates the USB bus status and the presence or absence of register data.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 2)
and the current setting of the interface.
n = 2 to 0
7
0
HALTn
Bit name
6
0
CHAPTER 12 USB FUNCTION CONTROLLER (USBF)
These bits indicate that Endpoint n is currently stalled. These bits are set to 1 when a
stall condition, such as occurrence of an overrun and reception of an undefined request,
is satisfied. These bits are automatically set to 1 by hardware.
The SNDSTL bit is set to 1 as soon as the HALT0 bit has been set to 1 as a result of
occurrence of an overrun or reception of an undefined request. If the next SETUP token
is received in this status, the SNDSTL bit is cleared to 0 and, therefore, the HALT0 bit is
also cleared to 0. If Endpoint0 is stalled by the SET_FEATURE Endpoint0 request, this
bit is not cleared to 0 until the CLEAR_FEATURE Endpoint0 request is received or Halt
Feature is cleared by FW. If the GET_STATUS Endpoint0, CLEAR_FEATURE
Endpoint0, or SET_FEATURE Endpoint0 request is received, or if a request to be
processed by FW is received due to the CPUDEC interrupt request, the HALT0 bit is
masked and cleared to 0, until the next SETUP token is received.
The HALTn bit is not cleared to 0 until Endpoint n receives the CLEAR_FEATURE
Endpoint request, Halt Feature is cleared by the SET_INTERFACE or
SET_CONFIGURATION request to the interface to which the endpoint is linked, or Halt
Feature is cleared by FW. When the SET_INTERFACE or SET_CONFIGURATION
request is correctly processed, the Halt Feature of all the target endpoints, except
Endpoint0, is cleared after the request has been processed, even if the wValue is the
same as the currently set value, and these bits are also cleared to 0. Halt Feature of
Endpoint0 cannot be cleared if it is set because the STALL response is made in
response to the SET_INTERFACE and SET_CONFIGURATION requests.
5
0
1: Endpoint is stalled.
0: Endpoint is not stalled (default value).
Preliminary User’s Manual U19014EJ1V0UD
4
0
3
0
HALT2
2
Function
HALT1
1
HALT0
0
Address
FF69H
After reset
00H
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