upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 448

• Manufacturer Part Number: upd78f0730
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Renesas Electronics Corporation.

18.2
448
Address: 0080H/1080H
The format of the option byte is shown below.
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
Cautions 1. The watchdog timer does not stop during self-programming of the flash memory and
Remarks 1.
Format of Option Byte
boot swap operation.
2.
2. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
3. Be sure to clear bit 7 to 0.
WINDOW1
LSROSC
WDTON
WDCS2
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time taking this delay into consideration.
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
f
( ): f
RL
7
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
1
: Internal low-speed oscillation clock frequency
RL
Note
= 264 kHz (MAX.)
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
WINDOW0
WINDOW1
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
Figure 18-1. Format of Option Byte (1/2)
Setting prohibited
100%
WINDOW0
Operation control of watchdog timer counter/illegal access detection
Preliminary User’s Manual U19014EJ1V0UD
WDCS0
CHAPTER 18 OPTION BYTE
5
0
1
0
1
0
1
0
1
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
Internal low-speed oscillator operation
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
4
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
WDCS1
2
WDCS0
1
LSROSC
0