upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 432
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upd78f0730
Manufacturer Part Number
upd78f0730
Description
8-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0730.pdf
(518 pages)
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In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
432
Supply voltage
oscillation clock (f
(when X1 oscillation
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 17
Remarks 1. V
Internal reset signal
Internal high-speed
system clock (f
(V
V
POC
DD
High-speed
is selected)
)
= 1.59 V (TYP.)
2.
1.8 V
2.7 V (TYP.)
CPU
LOW-VOLTAGE DETECTOR).
Figure 16-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
RH
XH
2. V
3. For the
Note 1
V
0 V
The operation guaranteed range is 1.8 V ≤ V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock can be selected as the CPU
clock. To use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization
time.
)
)
LVI
Operation
(POCMODE = 1).
LVI
POC
stops
:
:
µ
LVI detection voltage
POC detection voltage
PD78F0730, be sure to set the 2.7 V/1.59 V POC mode by using the option byte
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
Set LVI to be
used for reset
CHAPTER 16 POWER-ON-CLEAR CIRCUIT
specified by software.
oscillation clock)
(internal high-speed
Starting oscillation is
Normal operation
Preliminary User’s Manual U19014EJ1V0UD
µ
and Low-Voltage Detector
Note 2
Reset period
(oscillation
stop)
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
used for interrupt
Set LVI to be
DD
oscillation clock)
(internal high-speed
Normal operation
≤ 5.5 V. To make the state at lower than 1.8 V reset
specified by software.
Starting oscillation is
µ
Note 2
Reset period
(oscillation
stop)
Reset processing (20 s (TYP.))
Wait for oscillation
accuracy
stabilization
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
µ
Note 2
Operation stops
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