cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 130

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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UART/IR Controller Functional Description
Timeout Conditions for UART, SIR, and Sharp-IR
Modes
RX_FIFO timeout conditions:
• At least one byte is in the RX_FIFO.
• More than four character times have elapsed since the
• More than four character times have elapsed since the
Timeout Conditions for CEIR Mode
The RX_FIFO timeout in CEIR mode is disabled while the
receiver is active. The conditions for this timeout to occur
are as follows:
• At least one byte has been in the RX_FIFO for 64 µs or
• The receiver has been inactive (RXACT = 0) for 64 µs or
• More than 64 µs have elapsed since the last byte was
4.11.1.6 Transmit Deferral
This feature allows software to send short, high-speed data
frames in PIO mode without the risk of generating a trans-
mitter underrun.
Transmit deferral is available only in extended mode and
when the TX_FIFO is enabled. When transmit deferral is
enabled (TX_DFR bit of the MCR register set to 1) and the
transmitter becomes empty, an internal flag is set and locks
the transmitter. If the processor now writes data into the
TX_FIFO, the transmitter does not start sending the data
until the TX_FIFO level reaches either 14 for a 16-level
TX_FIFO or 30 for a 32-level TX_FIFO, at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a timeout condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
The timeout mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO, the timer is reloaded with the initial value. If
no byte is loaded for a 64 µs time, the timer times out and
the internal flag is cleared, thus enabling the transmitter.
4.11.1.7 Automatic Fallback to 16550 Compatibility
This feature is designed to support existing legacy software
packages, using the 16550 serial port. For proper opera-
tion, many of these software packages require that the
module look identical to a plain 16550, since they access
the serial port registers directly. Because several extended
features and new operational modes are provided, make
sure the module is in the proper state before executing a
legacy program.
last byte was loaded into the RX_FIFO from the receiver
logic.
last byte was read from the RX_FIFO by the processor
or DMA controller.
more.
more.
read from the RX_FIFO by the processor or DMA
controller.
Mode
130
(Continued)
The fallback mechanism eliminates the need to change the
state when a legacy program is executed following comple-
tion of a program that used extended features. It automati-
cally switches the module to 16550 compatibility mode and
turns off any extended features whenever the Baud Gener-
ator Divisor Register is accessed through the LBGD_L or
LBGD_H ports in register Bank 1.
In order to avoid spurious fallbacks, baud generator divisor
ports are provided in Bank 2. Baud generator divisor
access through these ports changes the baud rate setting
but does not cause fallback.
New programs designed to take advantage of the extended
features should not use LBGD_L and LBGD_H to change
the baud rate. Instead, they should use BGD_L and
BGD_H.
A fallback can occur in either extended or non-extended
modes. If extended mode is selected, fallback is always
enabled. In this case, when a fallback occurs, the following
happens:
• TX_FIFO and RX_FIFO switch to 16 levels.
• A value of 13 is selected for the baud generator pre-
• ETDLBK and BTEST of the EXCR1 register are cleared.
• UART mode is selected.
• The functional block switches to non-extended mode.
When fallback occurs from non-extended mode, only the
first three of the above actions occur. If either Sharp-IR or
SIR infrared modes were selected, no switching to UART
mode occurs. This prevents spurious switching to UART
mode when a legacy program, running in Infrared mode,
accesses the Baud Generator Divisor Register from Bank
1.
Fallback from non-extended mode can be disabled by set-
ting LOCK in the EXCR2 register to 1. When LOCK is set
and the functional block is in non-extended mode, two
scratch pad registers overlaid with LBGD_L and LBGD_H
are enabled. Any attempted processor access of the Baud
Generator Divisor Register through LBGD_L and LBGD_H
accesses the scratch pad registers, without affecting the
baud rate setting. This feature allows existing legacy pro-
grams to run faster than 115.2 kbaud, without realizing they
are running at this speed.
4.11.2 Modem Support
An MSR (MSR_UART[x]_MOD) (UART1 MSR 51400038h
and UART2 MSR 5140003Ch) mimics modem input sig-
nals for making it compatible with the software having
modem support. The hardware of this module has all the
required functionality for modem compatibility.
scaler.
Revision 0.8