cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 167

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
PMC Functional Description
Event
GPE[23:0]
(General Purpose
Power Manage-
ment Events in
Working Domain)
GPE[31:24]
(General Purpose
Power Manage-
ment Events in
Standby Domain)
The following events caused a Standby state entry.
RESET_STAND#
LVD circuit detects
low voltage on
V
PWR_BTN#
THRM_ALRM#
CORE
Current
State
Working
Sleep
Working
Sleep
Standby
Working
Sleep
Standby
Working
Sleep
Standby
Working
Sleep
Standby
Working
Sleep
Standby
Table 4-35. PM Events and Functions (Continued)
Function
If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), the corresponding
status bit (GPE_STS[23:0]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an
SCI is generated.
If GPE_EN[23:0] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and
wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset
00h[15] = 1).
If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding
status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set and an
SCI is generated.
If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[23:0] = 1), SCI generation and
wakeup from the event is enabled (i.e., sets the WAK_STS bit, ACPI I/O Offset
00h[15] = 1).
If GPE_EN[31:24] are enabled (ACPI I/O Offset 1Ch[31:24] = 1), the corresponding
status bit (GPE_STS[31:24]) in GPE0_STS (ACPI I/O Offset 18h[23:0]) is set, and
SCI generation and wakeup from the event is enabled (i.e., sets the WAK_STS bit,
ACPI I/O Offset 00h[15] = 1).
If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset
54h[0]) is set and causes a Reset Standby state entry. No Working or Standby
power.
If asserted, the corresponding status bit (OFF_FLAG) in PM_SSC (PMS I/O Offset
54h[0]) is set and causes a Reset Standby state entry. No Working or Standby
power.
If asserted in Restart, or Normal or Faulted Standby state, the corresponding status
bit (OFF_FLAG) in PM_SSC (PMS I/O Offset 54h[0]) is set and causes a Reset
Standby state entry.
If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set
and causes an Faulted Standby state entry. Working power is turned-off.
If de-asserted, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Offset 54h[2]) is set
and causes an Faulted Standby state entry. Working power is turned-off.
If de-asserted in Restart state, the status bit (LVD_FLAG) in PM_SSC (PMS I/O Off-
set 54h[2]) is set and causes an Faulted Standby state entry.
If enabled and asserted for four seconds (fail-safe), the status bit (PWRBUT_FLAG)
in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state
entry. Working power is turned-off.
If enabled and asserted for four seconds (fail-safe), the status bit (PWRBUT_FLAG)
in PM_SSC (PMS I/O Offset 54h[3]) is set and causes an Faulted Standby state
entry. Working power is turned-off.
If enabled and asserted for four seconds (fail-safe) while in Normal or Restart state,
the status bit (PWRBUT_FLAG) in PM_SSC (PMS I/O Offset 54h[3]) is set and
causes a Faulted Standby state entry.
If enabled and asserted for a programmable amount of time, the status bit
(THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted
Standby state entry. Working power is turned-off.
If enabled and asserted for a programmable amount of time, the status bit
(THRM_FLAG) in PM_SSC (PMS I/O Offset 54h[4]) is set and causes an Faulted
Standby state entry. Working power is turned-off.
If asserted in Normal or Re-start state, the status bit (THRM_FLAG) in PM_SSC
(PMS I/O Offset 54h[4]) is set and causes a Faulted state entry.
(Continued)
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