cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 347

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
5.10 KEYBOARD EMULATION LOGIC REGISTER DESCRIPTIONS
The registers for the Keyboard Emulation Logic (KEL) are
divided into three sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• KEL Specific MSRs
• KEL Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
All MSRs are 64 bits, however, the KEL Specific MSRs are
called out as 32 bits. The KEL treats writes to the upper 32
bits (i.e., bits [63:32]) of the 64-bit MSRs as don’t cares and
always returns 0 on these bits. The KEL Specific MSRs are
summarized in Table 5-24.
Four Native registers are used to provide the keyboard
emulation support, summarized in Table 5-25:
• KEL HCE Control Register: Used to enable and control
MSR Address
060h
060h
064h
064h
KEL Memory
Port
see Section 5.6.1 on page 299.)
the emulation hardware and report various status infor-
mation.
5140001Fh
I/O
Offset
10Ch
100h
104h
108h
092h
Cycle
Read
Write
Read
Write
I/O
Accessed/Modified Side Effects in Emulation Mode
Register Contents
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
HCE_Output
HCE_Status
HCE_Input
HCE_Input
Table 5-26. KEL Legacy Registers Emulated Summary
Register Name
Keyboard Emulation Logic Control Register
(KELX_CTL)
Width
(Bits)
32
32
32
32
8
Table 5-25. KEL Native Registers Summary
Table 5-24. KEL Specific MSRs Summary
Register Name
KEL HCE Control Register
(KEL_HCE_CTRL)
KEL HCE Input (KEL_HCE_IN)
KEL HCE Output (KEL_HCE_OUT)
KEL HCE Status (KEL_HCE_STS)
Port A (KEL_PORTA)
Read from Port 060h clears OutputFull in HCE_Status to 0.
Write to Port 060h sets InputFull to 1 and CmdData to 0 in HCE_Status.
Read from Port 064h returns current value of HCE_Status with no side effects.
Write to Port 064h will set InputFull to 0 and CmdData in HCE_Status to 1.
347
• KEL HCE Input Register: Emulation side of the legacy
• KEL HCE Output Register: Emulation side of the
• KEL HCE Status Register: Emulation side of the
Each of the Native registers is located on a 32-bit bound-
ary. The Offset of these registers is relative to the base
address. (See Section 5.6.2.2 "Local BAR - KEL from USB
Host Controller 1 (DIVIL_LBAR_KEL1)" on page 308 and
Section 5.6.2.3 "Local BAR - KEL from USB Host Control-
ler 2 (DIVIL_LBAR_KEL2)" on page 308.) Any writes to
locations outside these offsets are a “don’t care”. Any
reads to locations outside these offsets return zero.
Three
HCE_Input, HCE_Output), summarized in Table 5-25, are
accessible at I/O Port 060h and 064h when emulation is
enabled. Port A is at I/O Port 092h. Reads and writes to the
registers using I/O addresses have side effects as outlined
in Table 5-26.
8048 Controller Input Buffer register. Writes to I/O Port
060h and 064h are read here.
legacy 8048 Controller Output Buffer register where
keyboard and mouse data is to be written by software.
Reads from I/O Port 060h are setup here.
legacy 8048 Controller Status register. Reads from I/O
Port 60h are setup here.
of
the
operational
Reset Value
Reset Value
00000010h
00000000h
000000xxh
000000xxh
00000000h
00h
registers
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(HCE_Status,
Reference
Reference
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