cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 160

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PMC Functional Description
4.17.2.1 ACPI System Power States
• G0/S0: Not Sleeping. Software is executing code or
• G1/S1: Requires explicit software action to enter this
• G1/S3: Save-to-RAM state. Requires explicit software
• G1/S4: Suspend-to-Disk state. Requires explicit soft-
• G2/S5: Requires explicit software action to enter this
• G3: Software action is not required to enter this state.
4.17.2.2 CPU Power States
• G0/S0/C0: Processor actively executing instructions and
• G0/S0/C1: HLT instruction executed. Usually occurs in
could be halted waiting for a system event.
state. All GX2, CS5535, and main memory states main-
tained. All system clocks may be turned off except 32
kHz or selected additional clocks may be left on as
required. The PMC provides generic controls SLEEP_X
and SLEEP_Y that may be used to control the “D” states
of external system devices (not described in this
datasheet, see ACPI specification for details). Two addi-
tional internal signals control PCI and IDE input and
outputs. A wakeup event brings the system back to the
opcode following the one that initiated entry into S1.
Context restore operation is not required on the GX2,
CS5535, or main memory.
action to enter this state. The CS5535 and other system
context are lost. System state is saved in the main
memory. To properly support this state, main memory
power must be controlled by WORKING power while the
CS5535, GX2, and all other system components power
must be controlled by WORK_AUX power. Note that this
applies only to the Working domain of the CS5535. The
Standby domain must be continuously supplied from
Standby power.
ware action to enter this state. Same as S3 state, but the
system state is “saved” on the hard drive or other mass
storage device. Only Standby power is on while in this
state.
state. All system context is lost and not saved. Operating
system re-boot is required. The 32 kHz clock is kept
running for Standby PMC and selected GPIO and
MFGPT circuits.
Working power and Standby power are removed. The
only domain that may be powered is the RTC. It is not a
requirement that the RTC be powered.
clock running. Cache snoops supported.
the Operating System’s idle loop. Operating System
waiting for Power Management Event (PME), interrupt,
or ASMI. Cache snoops are supported while in this
state, so bus mastering activity can safely occur.
(Continued)
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• G1/S1/C2: Processor is in the lowest power state that
4.17.2.3 Hardware Power States
• FO (Full On): From a hardware reset, all clocks come
• AHCG (Active Hardware Clock Gating): This is the
• Suspend on Halt: See CPU power state G0/S0/C1.
• Sleep: See CPU power state G1/S1/C2.
• Auto-refresh: The memory controller issues an auto-
4.17.2.4 PMC Control
Under S3, S4, and S5 power management states, all Work-
ing domain circuits, as well as the GX2, are turned off to
conserve power. Under S3, the system memory is powered
by V
other system components are also turned off.
The PMC is used to establish overall system power states.
Normally, the Standby domain voltages are present any-
time the system is plugged into the wall; if portable, any-
time the battery is plugged in. Generally, G3 Mechanical
Off (see Table 4-34 on page 159) only applies during stor-
age or maintenance. Therefore, operationally speaking, the
PMC Standby controller is always available to manage
power. There is a class of system designs that do not
require G1 and G2 global power states. These systems
usually power-up WORKING and STANDBY power
domains simultaneously when power is applied.
For supporting “Save-to-RAM” (G1/S3) the WORKING out-
put is used to switch off/on the Working domain sources for
system memory while the WORK_AUX output is used to
switch off/on the Working domain sources for everything
else. Thus, the PMC can completely control the system
power states via these outputs.
maintains context in a software invisible fashion. Entered
as part of the S1 sequence. The SUSP#/SUSPA#
signaling protocol indicates entry. SUSP# is not an
explicit external signal, it is part of the CIS packet. (See
Section 4.2.14 "CPU Interface Serial (CIS)" on page 79
for further details.) No explicit software action required.
However, this state can be entered by explicit software
action by reading the ACPI P_LVL2 register provided by
the GX2 GLCP.
up Full On or always running. Generally, the system
should not be left in this state. The AHCG state should
be used.
desired mode of operation; it utilizes automatic hardware
clock gating. Latency to turn on a clock is near 0. This
hardware state should be established at system initial-
ization by BIOS code; after initialization it needs no addi-
tional support. AHCG is invisible to the Operating
System, ACPI, or other software based power manage-
ment facilities.
refresh command to the DRAMs. In this state, the
DRAMs perform refresh cycles on their own without any
additional commands or activity from the memory
controller or the interface. As long as power to the
DRAMs is maintained, the memory contents are
retained.
IO_VSB
in Standby Auto-refresh mode but otherwise, all
Revision 0.8