cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 53

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Global Concepts and Features
In addition to the “positive” address decode above, each
GLIU has a subtractive port that takes all addresses not
assigned to a specific port. There is always a default sub-
tractive port path to the boot ROM to allow the central pro-
cessor to start executing code from time zero. Thus, from
system reset, there is a default memory address path that
allows the first processor instruction fetch to:
1)
2)
3)
4)
3.1.7
The BIZZARO flag is used to indicate special cycles and
exceptions to normal packet operation. All special cycles
traverse the GLIU system as I/O packets with the BIZZARO
flag set. The special cycles are:
1)
2)
3)
3.2
An MSR address consists of the fields shown in Table 3-1.
When a GLIU receives an MSR packet, it routes the packet
to the port specified in Field 0 but shifts address bits
[31:14] to the left by three bits and replaces bits [16:14]
with zero. Thus, Field 1 is moved to Field 0, Field 2 is
moved to Field 1, etc. The address field always remains
unchanged and selects one 64-bit MSR per address value,
Routing
Proceed down through the two GX2 GLIUs;
cross the PCI bus to the CS5535;
proceed down through the CS5535 GLIU to the default
port connected to the DD; and
access the boot device connected to the DD.
Interrupt Acknowledge: I/O read from address zero.
Shutdown: I/O write to address zero.
Halt: I/O write to address one.
Field 0
[31:29]
CS5535 MSR ADDRESSING
Bits
Special Cycles and BIZZARO Flag
Routing
Field 1
[28:26]
Bits
Routing
Field 2
[25:23]
Bits
Table 3-1. MSR Routing Conventions
(Continued)
Routing
Field 3
[22:20]
Bits
53
that is, the address value 0 accesses one 64-bit register,
the address value 1 accesses one 64-bit register, the
address value 2 accesses one 64-bit register, etc. There
are no MSR byte enables. All 64 bits are always written and
read.
Many CS5535 MSRs are only 32 bits in physical size. In
these cases, interface logic discards the upper 32 bits on
writes and pads the upper 32 bits on reads. Read padding
is undefined. Lastly, CS5535 GLDs only decode enough
bits of the address to select one of N MSRs, where N is the
total number of MSRs in the device. For example, if a GLD
has only 16 MSRs, then the addresses 0x2001, 0x0201,
0x0021, and 0x0x0001 all access MSR number 1, while the
addresses 0x200F, 0x020F, 0x002F, and 0x0x000F all
access MSR number 15.
To access a given GLD, use Table 3-2 "CS5535 MSR
Addresses from GX2 Processor" on page 54. Note the tar-
get device addresses:
The xxxx portion refers to the MSR addresses as they
appear any place within Section 5.0 "Register Descrip-
tions" on page 184. To form a complete MSR address,
“OR” an address provided in a register description section
with the appropriate address above.
Routing
Field 4
[19:17]
Bits
GLPCI_SB
GLIU
USBC2
ATAC
DD
ACC
USBC1
GLCP
Routing
Field 5
[16:14]
Bits
5100xxxxh
5101xxxxh
5120xxxxh
5130xxxxh
5140xxxxh
5150xxxxh
5160xxxxh
5170xxxxh
Address
[13:0]
Field
Bits
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