cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 494

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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PMC Register Descriptions
5.18.3.12 PM De-assert Reset Delay from Standby (PM_RD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
29:20
19:0
Bit
Bit
30
31
30
Name
WORK_AUX_
DEASSERT_EN
RSVD
WORK_AUX_
DEASSERT_
DELAY
Name
RESET_LOCK
RESET_EN
RSVD
38h
R/W
40000100h
RSVD
Description
Working Auxiliary De-assert and Delay Enable. Must be high to de-assert the
WORK_AUX output and enable its delay specified in bits [19:0]
(WORK_AUX_DEASSERT_DELAY).
Use of this control implies a system sequence into the Standby State. The PMC dis-
ables its interfaces to non-Standby portions of the component and only considers
wakeup events from Standby circuits. The PMC also immediately asserts system reset
when SLP_CLK_EN# is asserted regardless of the value of
WORK_AUX_DEASSERT_DELAY (bits [19:0]). Reset remains asserted throughout
the Standby state.
There is NOT an assert delay. The wakeup event causes the WORK_AUX output to
assert. This event is called Standby wakeup.
On wakeup, Reset continues to be applied to all non-Standby circuits for the length of
time specified in RESET_DELAY (PMS I/O Offset 38h[19:0]).
Enabling this function and/or the function in PM_WKD (PMS I/O Offset 30h[30] = 1)
causes the same Standby state events. Standby state is not entered unless
SLP_CLK_EN# is asserted.
Reserved. By convention write 0, but may write anything. Reads return 0.
WORK_AUX De-assert Delay. Indicates the number of 32 kHz clock edges to wait
from the assertion of SLP_CLK_EN# before de-asserting the WORK_AUX output. Bit
30 (WORK_AUX_DEASSERT_EN) must be high to enable this delay.
Description
Reset Lock. After this bit is set, the value in this register can not be changed until
RESET_STAND# is applied.
Reset Delay Enable. Must be high for the RESET_OUT# output de-assert delay spec-
ified in bits [19:0] (RESET_DELAY) to be applied. (Default = 1.)
Reserved. By convention write 0, but may write anything. Reads return 0.
(Continued)
PM_WKXD Bit Descriptions
PM_RD Bit Descriptions
PM_RD Register Map
494
RESET_DELAY
9
8
7
6
5
4
3
2
Revision 0.8
1
0