cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 373

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
UART/IR Controller Register Descriptions
5.12.3.4
These registers share the same address.
The Link Control Register (LCR) selects the communication format for data transfers in UART, SIR and Sharp-IR modes.
The Bank Select Register (BSR) is used to select the register bank to be accessed next.
Reading the register at this address location returns the content of the BSR. The content of LCR can be read from the
Shadow of Link Control register (SH_LCR) in Bank 3, I/O Offset 01h (see Section 5.12.6.2 on page 388). During a write
operation to this register at this address location, setting of Bank Select Enable (BKSE, bit 7) determines the register to be
accessed, as follows:
• If bit 7 is 0, both LCR and BSR are written into.
• If bit 7 is 1, only BSR is written into and LCR remains unchanged. This prevents the communication format from being
Link Control Register (LCR)
I/O Offset
Type
Reset Value
Bits 6 to 0 are only effective in UART, Sharp-IR and SIR modes. They are ignored in CEIR mode.
spuriously affected when a bank other than Bank 0 or 1 is accessed.
Bit
7
6
5
4
3
BKSE
7
Link Control/Bank Select Registers
Name
BKSE
SBRK
STKP
EPS
PEN
03h
WO
00h
SBRK
6
Description
Bank Select Enable.
0: Register functions as the Link Control register (LCR).
1: Register functions as the Bank Select register (BSR).
Set Break. Enables or disables a break. During the break, the transmitter can be used as a
character timer to accurately establish the break duration. This bit acts only on the trans-
mitter front end and has no effect on the rest of the transmitter logic. When set to 1, the fol-
lowing occurs:
To avoid transmission of erroneous characters as a result of the break, use the following
procedure:
Stick Parity. When parity is enabled (PEN is 1), this bit and EPS (bit 4) control the parity
bit (see Table 5-59). This bit has no effect when parity is not enabled.
Even Parity Select. When parity is enabled (PEN is 1), this bit and STKP (bit 5) control the
parity bit (see Table 5-59). This bit has no effect when parity is not enabled.
Parity Enable. This bit enables the parity bit. The parity enable bit is used to produce an
even or odd number of 1s when the data bits and parity bit are summed, as an error detec-
tion device.
0: No parity bit is used (Default).
1: A parity bit is generated by the transmitter and checked by the receiver.
— If UART mode is selected, the UART[x]_TX pin is forced to a logic 0 state.
— If SIR mode is selected, pulses are issued continuously on the UART[x]_IR_TX pin.
— If Sharp-IR mode is selected and internal modulation is enabled, pulses are issued
— If Sharp-IR mode is selected and internal modulation is disabled, the
— Wait for the transmitter to be empty (TXEMP = 1).
— Set SBRK to 1.
— Wait for the transmitter to be empty, and clear SBRK to restore normal transmission.
STKP
continuously on the UART[x]_IR_TX pin.
UART[x]_IR_TX pin is forced to a logic 1 state.
5
LCR Bit Descriptions
LCR Register Map
EPS
4
373
(Continued)
PEN
3
STB
2
1
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