cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 378

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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UART/IR Controller Register Descriptions
Bit
7
6
5
4
3
2
1
0
Name
ER_INF
TXEMP
TXRDY
BRK
FE
PE
OE
RXDA
Description
Error in RX_FIFO. In UART, Sharp-IR, and SIR modes, this bit is set to 1 if there is at least
one framing error, parity error, or break indication in the RX_FIFO. This bit is always 0 in
16450 mode. It is cleared upon read or upon reset if there is no faulted byte in RX_FIFO.
Transmitter Empty. This bit is set to 1 when the transmitter holding register or the
TX_FIFO is empty, and the transmitter front end is idle.
Transmitter Ready. This bit is set to 1 when the transmitter holding register or the
TX_FIFO is empty. It is cleared when a data character is written to the TXD register.
Break Event Detected. In UART, Sharp-IR, and SIR modes, this bit is set to 1 when a
break event is detected (i.e., when a sequence of logic 0 bits, equal or longer than a full
character transmission, is received). If the FIFOs are enabled, the break condition is asso-
ciated with the particular character in the RX_FIFO to which it applies. In this case, the
BRK bit is set when the character reaches the bottom of the RX_FIFO. When a break event
occurs, only one 0 character is transferred to the receiver holding register or the RX_FIFO.
The next character transfer takes place after at least one logic 1 bit is received, followed by
a valid start bit. This bit is cleared upon read.
Framing Error. In UART, Sharp-IR and SIR modes, this bit is set to 1 when the received
data character does not have a valid stop bit (i.e., the stop bit following the last data bit or
parity bit is a 0). If the FIFOs are enabled, this Framing Error is associated with the particu-
lar character in the FIFO it applies to. This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO. After a framing error is detected, the receiver
will try to resynchronize. The receiver assumes that framing error (the erroneous stop bit) is
the next start bit (the erroneous stop bit) and shifts in the new character. This bit is cleared
upon a read.
Parity Error. In UART, Sharp-IR, and SIR modes, this bit is set to 1 if the received data
character does not have the correct parity, even or odd, as selected by the parity control
bits of the LCR. If the FIFOs are enabled, this error is associated with the particular charac-
ter in the FIFO that it applies to. This error is revealed to the CPU when its associated char-
acter is at the bottom of the RX_FIFO. This bit is cleared upon read.
Overrun Error. In UART, Sharp-IR, and SIR modes, this bit is set to 1 as soon as an over-
run condition is detected by the receiver. It is cleared upon read.
FIFOs Disabled: An overrun occurs when a new character is completely received into the
receiver front end section and the CPU has not yet read the previous character in the
receiver holding register. The new character overwrites the previous character in the
receiver holding register.
FIFOs Enabled: An overrun occurs when a new character is completely received into the
receiver front end section and the RX_FIFO is full. The new character is discarded, and the
RX_FIFO is not affected.
Receiver Data Available. This bit is set to 1 when the receiver holding register is full. If the
FIFOs are enabled, this bit is set when at least one character is in the RX_FIFO. It is
cleared when the CPU reads all the data in the holding register or the RX_FIFO.
LSR Bit Descriptions
378
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Revision 0.8