cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 427

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cs5535

Manufacturer Part Number
cs5535
Description
Geode Cs5535 Companion Multi-function South Bridge
Manufacturer
National Semiconductor Corporation
Datasheet

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Revision 0.8
RTC Register Descriptions
5.15.2.10 Year (RTC_YEAR)
I/O Address
Type
Reset Value
5.15.2.11 RTC Control Register A (RTC_CRA)
I/O Address
Type
Reset Value
This register controls test selection among other functions. This register cannot be written before reading bit 7 of RTC_CRD
(VRT bit).
Bit
7:0
Bit
6:4
3:0
7
UIP
7
7
Name
YR_DATA
Name
UIP (RO)
DIV_CHN_CTL
PIR_SEL
09h
R/W
00h
0Ah
R/W
20h
6
6
DIV_CHN_CTL
Description
Year Data. This register holds the two least significant digits of a four-digit year. For
example, if the year is 2007, this register would contain the equivalent of ‘07’. Values
may be 00 to 99 in BCD format or 00 to 63 in binary format. Reset by V
Description
Update in Progress (Read Only). This RO bit is not affected by reset. This bit reads 0
when bit 7 of RTC_CRB is 1.
0: Timing registers not updated within 244 µs.
1: Timing registers updated within 244 µs.
Divider Chain Control. These R/W bits control the configuration of the divider chain for
timing generation and register bank selection. They are cleared to 010 as long as bit 7
of RTC_CRD (VRT bit) is 0.
00x: Oscillator Disabled.
010: Normal Operation.
011: Test.
Periodic Interrupt Rate Select: These R/W bits select one of fifteen output taps from
the clock divider chain to control the rate of the periodic interrupt. They are cleared to
000 as long as bit 7 of RTC_CRD (VRT bit) is 0.
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
5
5
(Continued)
No interrupts
3.906250 ms
7.812500 ms
0.122070 ms
0.244141 ms
0.488281 ms
0.976562 ms
1.953125 ms
RTC_CRA Bit Descriptions
RTC_YR Bit Descriptions
RTC_CRA Register Map
RTC_YR Register Map
4
4
YR_DATA
427
3
3
10x: Test.
11x: Divider Chain Reset.
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
3.906250 ms
7.812500 ms
15.625000 ms
31.250000 ms
62.500000 ms
125.000000 ms
250.000000 ms
500.000000 ms
2
2
PIR_SEL
1
1
PP
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