cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 477

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
5.18 POWER MANAGEMENT CONTROLLER REGISTER DESCRIPTIONS
The registers for the Power Management Controller (PMC)
are divided into four sets:
• Standard GeodeLink Device MSRs (Shared with DIVIL,
• PMC Specific MSRs
• ACPI Registers
• PM Support Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 3.2 "CS5535
MSR Addressing" on page 53 for more details on MSR
addressing.
All MSRs are 64 bits, however, the PMC Specific MSRs
(summarized in Table 5-66) are called out as 32 bits. The
PMC module treats writes to the upper 32 bits (i.e., bits
Note 1. Required ACPI register.
Note 2. Both PM1_STS and PM1_EN access Offset 00h when using 32-bit access.
Note 3. SSMI may be implemented on this register by decode hardware outside of PM module.
Note 4. Optional ACPI register. SSMI may be implemented on this register by decode hardware outside of PM module.
Note 5. Required ACPI register that can also be implemented via a control method.
51400050h
51400051h
I/O Offset
Address
see Section 5.6.1 on page 299.)
ACPI
MSR
0Ch
1Ch
00h
02h
08h
10h
14h
18h
Only PM1_STS with a 16-bit access to Offset 00h.
Only PM1_EN with a 16-bit access to Offset 02h.
Offset 04h is reserved. Reads return 0.
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Register Name
PMC Logic Timer (PMC_LTMR)
PMC Reserved (PMC_RSVD)
Width
(Bits)
16
16
16
16
32
32
32
32
Register Name
PM Status 1 (PM1_STS) (Note 1 and
Note 2)
PM Enable 1 (PM1_EN) (Note 1 and
Note 2)
PM Control 1 (PM1_CNT) (Note 1 and
Note 3)
PM Control 2 (PM2_CNT) (Note 4)
PM Timer (PM_TMR) (Note 1)
PM Reserved (PM_RSVD)
General Purpose Events Status 0
(PM_GPE0_STS) (Note 5)
General Purpose Events Enable 0
(PM_GPE0_EN) (Note 5)
Table 5-66. PMC Specific MSRs Summary
Table 5-67. ACPI Registers Summary
477
[63:32]) of the 64-bit MSRs as don’t cares and always
returns 0 on these bits.
The configuration registers associated with the PMC are
divided into two categories: ACPI registers (summarized in
Table 5-67) and PM Support registers (summarized in
Table 5-68 on page 478):
• The ACPI registers are accessed via Base Address
• The PM Support registers are accessed via a Base
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
Register, MSR_LBAR_ACPI (MSR 5140000Eh), as I/O
Offsets. (See Section 5.6.2.7 on page 311 for bit
descriptions of the Base Address Register.)
Address Register, MSR_LBAR_PMS (MSR
5140000Fh), as I/O Offsets. (See Section 5.6.2.8 on
page 312 for bit descriptions of the Base Address
Register.)
No f/flops
No f/flops
Domain
Working
Domain
Standby
Standby
Working
Working
Working
Standby
Standby
Power
Power
00000000h
00000000h
00000000h
00000000h
Reset
Reset
0000h
0100h
0000h
0000h
0000h
0000h
Value
Value
www.national.com
Reference
Reference
Page 479
Page 479
Page 479
Page 481
Page 481
Page 482
Page 483
Page 483
Page 485
---