cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 318
cs5535
Manufacturer Part Number
cs5535
Description
Geode Cs5535 Companion Multi-function South Bridge
Manufacturer
National Semiconductor Corporation
Datasheet
1.CS5535.pdf
(555 pages)
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DIVIL Register Descriptions
5.6.2.12
MSR Address
Type
Reset Value
5.6.2.13 Soft Reset (DIVIL_SOFT_RESET)
MSR Address
Type
Reset Value
5.6.2.14
MSR Address
Type
Reset Value
The controls below only affect memory and I/O accesses to the target slaves. MSR accesses are not affected. However,
MSR writes during DMA may have unintended side effects.
Note that when in demand or block mode, the UART reads and writes are disallowed; no corresponding mechanism exists
to allow UART controller reads or writes during UART activity. If attempted, CPU writes have no effect and the CPU reads
return all 1s.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:1
31:1
Bit
Bit
0
0
Soft IRQ (DIVIL_SOFT_IRQ)
Access Control DMA Request (DIVIL_AC_DMA)
Name
RSVD
SOFT_IRQ
Name
RSVD
SOFT_RESET
51400016h
R/W
00000000h
51400017h
R/W
00000000h
5140001Eh
R/W
00000000h
Description
Reserved. Reads return 0. Writes have no effect.
Soft IRQ. This bit can be written high or low. and is connected to the soft IRQ input of
the IRQ Mapper. Hence, writing high causes an interrupt while writing low clears it.
Reads return the value written.
Description
Reserved. Reads return 0. Writes have no effect.
Soft Reset. A bit that when written to a 1 causes the system to hard reset. Reads
return 0.
DIVIL_SOFT_RESET Bit Descriptions
(Continued)
DIVIL_SOFT_RESET Register Map
DIVIL_SOFT_IRQ Bit Descriptions
DIVIL_SOFT_IRQ Register Map
RSVD
RSVD
318
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
Revision 0.8
1
1
0
0
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