cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 57

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Global Concepts and Features
3.5
3.5.1
Table 3-3 lists the clock sources and domains.
Note 1.
Note 2.
Note 3.
Note 4.
Component Pin
MHZ66_CLK
Inverted MHZ66_CLK
(Note 1)
MHZ66_CLK divided by
two (Note 2)
PCI_CLK
MHZ48_CLK
MHZ48_CLK divided by
two (Note 2)
LPC_CLK
AC_CLK
MHZ14_CLK (Note 3)
KHZ32_XCI (Note 3)
TCK (Note 3)
(Note 4)
CLOCK CONSIDERATIONS
Clock Domain Definitions
The MHZ66_CLK is first inverted and then fed to all these domains.
Each domain receives the referenced clock and performs the divide just before the CCU.
This clock differs from other clocks in this table in that this clock does not utilize a CCU nor is it subject to GLCP control or power
management control.
This logic does not have a fixed clock source. During debug it is switched to the clock domain of interest. It does have a CCU.
Domain Name
ATAC_LB
GLIU_GLA
GLIU_STAT
GLPCI_GLIU
USBC2_GLIU
ATAC_GLIU
DD_GLIU
ACC_GLIU
USBC1_GLIU
GLCP_GLIU
USBC2_LB
ACC_LB
USBC1_LB
GLPCI_TRNA
GLPCI_INTF
GLCP_PCI
USBC#2_COR
USBC#1_COR
SMB_COR
UART1_COR
UART2_COR
DD_LB
LPC_COR
PIT_COR
DMA_COR
ACC_COR
MFGPT_COR_14M
PMC_SLP
PIT_REF
RTC_COR
MFGPT_COR_32K
MFGPT_COR_32K_S
PMC_STB
GPIO_COR
GPIO_COR_S
TAP_CNTRL
GLCP_DBG
Table 3-3. CS5535 Clock Sources and Clock Domains
(Continued)
Description
ATAC Local bus and ATAC core
GLIU GLA interface and related logic
GLIU Statistics Counters
GLPCI_SB GLIU interface and related logic
USBC2 GLIU interface and related logic
ATAC GLIU interface and related logic
DD GLIU interface and related logic
ACC GLIU interface and related logic
USBC1 GLIU interface and related logic
GLCP GLIU interface and related logic
USBC2 Local bus interface and related logic
ACC Local bus interface and related logic
USBC1 Local bus interface and related logic
GLPCI_SB transaction processing
GLPCI_SB interface to PCI bus
GLCP PCI related logic
USBC2 core logic
USBC1 core logic
System Management Bus core logic
UART1 core logic
UART2 core logic
DD Local bus interface and related logic; Includes PIC
LPC Controller core logic
Programmable Interval Timer core logic
8237 DMA core logic
ACC core logic
MFGPT core logic14 MHz clock
Power Management Controller Sleep logic
Programmable Interval Timer reference clock
RTC core logic
MFGPT core logic 32 kHz clock
MFGPT 32kHz clock source; Standby power domain
Power Management Controller Standby logic; Standby power domain
GPIO core logic
GPIO core logic; Standby power domain
JTAG TAP Controller clock source
GLCP debug logic
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