cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 367

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
UART/IR Controller Register Descriptions
5.12.3 Bank 0 Register Descriptions
In non-extended modes of operation, Bank 0 is compatible with both the 16450 and 16550. Upon reset, this functional block
defaults to the 16450 mode. In extended mode, all the registers (except RXD and TXD) offer additional features. The bit for-
mats for the registers in Bank 0 are summarized in Table 5-32. Detailed descriptions of each register follow.
Note 1. Non-Extended Mode.
Note 2. Extended Mode.
5.12.3.1
Receive Data Port (RXD)
I/O Offset
Type
Reset Value
Transmit Data Port (TXD)
I/O Offset
Type
Reset Value
The RXD (RO) and TXD (WO) ports share the same address.
RXD is accessed during CPU read cycles. It is used to receive incoming data when the FIFOs are disabled, or from the bot-
tom of the RX_FIFO when the FIFOs are enabled.
TXD is accessed during CPU write cycles. It is used to write data directly to the transmitter when the FIFOs are disabled, or
to the TX_FIFO when the FIFOs are enabled.
DMA cycles always access the TXD and RXD ports, regardless of the selected bank.
Offset Name
00h
00h
01h
02h
03h
04h
05h
06h
07h
I/O
RXD
TXD
IER
(Note 1)
IER
(Note 2)
EIR
(Note 1)
EIR
(Note 2)
FCR
LCR
BSR
MCR
(Note 1)
MCR
(Note 2)
LSR
MSR
SPR
(Note 1)
ASCR
(Note 2)
Receive/Transmit Data Ports
00h
RO
xxh
00h
WO
xxh
ER_INF
RXD7
BKSE
BKSE
TXD7
DCD
CTE
7
RXFTH[1:0]
FEN[1:0]
RSVD
RSVD
MDSL[2:0]
TXEMP
RXD6
SBRK
RSVD
TXUR
TXD6
RI
6
Table 5-32. Bank 0 Register Bit Map
RSVD
TXEMP_EV
TXEMP_IE
TXRDY
RXACT
RXD5
TXD5
STKP
DSR
5
TXFTH[1:0]
RSVD
367
(Continued)
DMA_EV
RXWDG
DMA_IE
IR_PLS
LOOP
RXD4
TXD4
EPS
BRK
CTS
4
Scratch Data
BSR[6:0]
TX_DFR
ISEN or
MS_EV
DCDLP
MS_IE
MS_IE
DDCD
RXD3
RSVD
RSVD
TXD3
RXFT
PEN
FE
3
TXHLT_EV
DMA_EN
LS_EV/
S_OET
LS_IE
LS_IE
RXD2
TXD2
TXSR
TERI
RILP
STB
PE
2
IPR[1:0]
TXLDL_EV
TXLDL_IE
TXLDL_IE
RXSR
DDSR
RSVD
RXD1
TXD1
RTS
RTS
OE
1
WLS[1:0]
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RXF_TOUT
RXHDL_IE
RXHDL_IE
RXHDL_IE
FIFO_EN
RXD0
RXDA
DCTS
TXD0
DTR
DTR
IPF
0