pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 106

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: PCI/XIO-16 Bus Interface Unit Capabilities
PNX17XX_SER_1
Preliminary data sheet
External Device
external PCI
master
external PCI slave 32-bit, up to 33 MHz
external 8-bit slave 8- and 16-bit wide,
standard (NOR)
Flash
NAND Flash
CIMaX device
1394 link core
DOCSIS devices
external SRAM,
ROM, EEPROM
Device Type
32-bit, up to 33 MHz
PCI masters
PCI targets
de-muxed address /
data devices on ‘XIO
bus’
8- and 16-bit wide
8- and 16-bit wide
8-bit data, 26-bit
address
8-bit data and 9-bit
address (Philips
PDI1394LXX)
8- and 16-bit wide
The table below summarizes extension capabilities of the bus interface unit.
Capabilities
Arbitration built-in for up to 3 external PCI masters. Additional external masters
can be supported with external arbitration. External PCI bus masters can
perform high bandwidth, low latency DMA into and out of PNX17xx Series
DRAM. Large block transfer capable devices can sustain up to 100 MB/s into
DRAM.
Glueless connection supported for multiple devices subject only to capacitive
loading constraints. The TM5250 can perform low-latency 8/16/32-bit writes and
reads to/from PCI targets. Access by TM5250 can be enabled or disabled.
Up to 5 devices supported gluelessly, or unlimited number subject to capacitive
loading rules with external address decode logic. The TM5250 can perform 8-.
16- or 32-bit reads and writes to these ‘XIO’ devices, which are automatically
mapped to 8- or 16 bit wide transfers by the bus interface unit.
Address range, and wait states for a Flash device are programmable. The
TM5250 can execute or read from Flash. Execution is low performance, and only
recommended for boot usage. The TM5250 can re-program Flash using special
software. Flash cannot be the target of a module DMA write - writes require a
software flash programming protocol.
Peak page mode read performance is at 66 MB/s for 16-bit devices and 33 MB/s
for 8-bit devices such as Intel StrataFlash (28FxxxJ3A, 32 Mbits, 64 Mbits, 128
Mbits) and ST MLC-NOR flash (M58LW064A, 64 Mbits). Cross-page random
read accesses each take 4 to 5 PCI clock cycles at 33 MHz depending on the
access-time of the device.
Flash is mostly active during system booting, or with low bandwidth during
system operation in order to implement a small non-volatile file system.
Direct execution, direct PI bus read or direct PI bus write from this Flash type are
not supported. Explicit programmed I/O through special NAND Flash PCI/XIO-8/
16 control/status registers is used to implement a file system on this disk-like
Flash type. Using the NAND-Flash XIO provisions, a peak bandwidth of 13
MB/s, and a sustained bandwidth of 11 MB/s can be obtained from a
AM30LV0064D 8Mx8 UltraNAND or equivalent Flash device. Maximum
throughput for serial burst accesses is 33 MB/s for 16-bit devices such as a
Samsung K9F5616U0B (16 Mbits x 16).
The external logic for conditional access consists of a CIMaX device, with 2
PCMCIA slot devices and glue logic (373, 245). This entire subsystem behaves
as an 8-bit wide slave with an up to 26-bit address space. This subsystem
interfaces gluelessly to the XIO bus, except for the possible logic needed to
combine the DTACK signalling of multiple devices.
There is medium bandwidth of communication between CIMaX and PNX17xx
Series, which is expected to not be an issue w.r.t. PCI performance.
The Philips PDI1394LXX family connects gluelessly to XIO in 8-bit data mode
using 8-bit data and 9-bit address with dedicated read and write strobes,
optional wait signal and a separate chip select. For systems which require high
asynchronous performance a 1394 link device with direct PCI connection can be
used.
Future DOCSIS devices are expected to be PCI bus mastering devices. They
connect gluelessly.
Counts as generic XIO slave device.
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 2: Overview
2-25