pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 301

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
PNX17XX_SER_1
Preliminary data sheet
7:0
Offset 0x10,4074-> 0x080
31:18
17:0
Offset 0x10,4084 -> 0x090
31:2
1:0
Offset 0x10,4094-> 0x0A0
31:2
1:0
Offset 0x10,40A4-> 0x0B0
31:20
13:0
Offset 0x10,40B4 -> 0x0C0
31:23
Bit
Symbol
IO_SEL_0
Unused
BUF_LEN
BASE1_PTR
Unused
BASE2_PTR
Unused
Unused
SIZE
Unused
PG_BUF_CTRL<0-3>
BASE2_PTR<0-3>
SIZE<0-3>
BASE1_PTR<0-3>
DIVIDER<0-3>
Acces
s
R/W
R/W
R/W
R/W
R/W
Value
0
-
0
0
-
0
-
-
0
-
Rev. 1 — 17 March 2006
Description
- In Signal Monitoring modes (FIFO_MODE[1]=0) this field selects
the GPIO pin or internal global signal to be observed. Refer to
Section 4.15
- In Pattern Generation modes (FIFO_MODE[1]=1) this field selects
the GPIO pin which is to be driven. Refer to
values.
This field indicates how many valid 32-bit words s/w has written to a
DMA buffer.
When BUF1_RDY is cleared the BUF_LEN value is loaded for DMA
buffer 1. When BUF2_RDY is cleared the BUF_LEN value is loaded
for DMA buffer 2.
The 18-bit field allows DMA buffer lengths as large as 1MB.
0x00000 - 1 32-bit word
0x00001 - 2 32-bit words
.....
0x3FFFF - 262143 32-bit words
Note: This field is valid in Pattern Generation modes
(FIFO_MODE[1]=1)
Start byte address for DMA buffer 1 of FIFO queue.
The base address must be 64-byte aligned.
Start byte address for DMA buffer 2 of FIFO queue.
The base address must be 64-byte aligned.
Size, in 64 bytes multiples, of each of the 2 DMA buffers:
0x0001 = 64 bytes
0x0002 = 128 bytes
....
0x3FFF = 1 Megabytes
for field values.
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Section 4.15
for field
8-30