pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 765

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
2.1.10 Modes of Operation
2.1.8 Data Shift Register
2.1.9 Related Interrupts
This register contains a byte of serial data to be transmitted or a byte which has just
been received. Like all the registers in this module, only bits 7-0 are used. Data in
DAT is always shifted from right to left; the first bit to be transmitted is the MSB (bit 7)
and, after a byte has been received, the first bit of received data is located at the MSB
(bit 7) of DAT. While data is being shifted out, data on the bus is simultaneously being
shifted in; DAT always contains the last byte present on the bus. Thus, in the event of
lost arbitration, the transition from master transmitter to slave receiver is made with
the correct data in DAT.
The serial interrupt signal (iic_intrn) issues an interrupt when any one of the 26
possible IIC module states are entered. The only state that never causes an interrupt
is state 0xF8, which indicates that no relevant state information is available.
The IIC module hardware may operate in any of the following four modes:
As a master, the IIC module will generate all the serial clock pulses and the START
and STOP conditions. A transfer ends with a STOP condition or with a repeated
START condition. Since a repeated START condition is also the beginning of the next
serial transfer, the I
Two types of data transfers are possible on the I
In a given application, the IIC module may operate as a master and as a slave. In the
slave mode, the IIC module hardware looks for its own slave address and the general
call address. If one of these addresses is detected, an interrupt is requested. When
the micro controller wishes to become the bus master, the hardware waits until the
bus is free before the master mode is entered so that a possible slave action is not
interrupted. If bus arbitration is lost in the master mode, the IIC module switches to
the slave mode immediately and can detect its own slave address in the same serial
transfer.
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Master Transmitter
Master Receiver
Slave Receiver
Slave Transmitter
Data transfer from a master transmitter to a slave receiver. The first byte
transmitted by the master is the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after each received byte.
Data transfer from a slave transmitter to a master receiver. The first byte (the
slave address) is transmitted by the master. The slave then returns an
acknowledge bit. Next follows the data bytes transmitted by the slave to the
master. The master returns an acknowledge bit after each received byte except
the last byte. At the end of the last received byte, a “not acknowledge” is returned.
Rev. 1 — 17 March 2006
2
C bus will not be released.
2
C bus:
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 25: I
2
C Interface
25-4