pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 816

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 7: DTL Interface Rules
Table 8: DCS Network Data Transfer Rules (32 Bits at-a-time Transfer)
PNX17XX_SER_1
Preliminary data sheet
Module
Item Unit
Size
8 bits
16 bits
16 bits
32 bits
32 bits
Module
Item Unit
Size
8 bits
8 bits
System
Endian Mode
either
big
little
big
little
System
Endian Mode DCS_D[31:24]
big
little
6.2.2 Address Invariant Data Ordering Rules
6.3 Data Transfers Across the DCS Network
The address invariance rule of the DTL interface is given in
implies the address, regardless of endian mode of the system.
Table 6: 32 Bit DTL Interface Byte Address
Modules dealing with 8, 16 or 32-bit units must place bytes on the DTL interface given
in
The DCS Network is said to be “endian neutral”. Although this bus is intended to
transfer mainly 32-bits of control and status data, it can carry smaller units of data
(8-bit, 16-bit for e.g., CPU accesses to PCI devices). Accesses on this bus are mainly
MMIO accesses. The only memory accesses allowed are for booting purposes via
the DCS Gate module. This is only accessed by the boot module. The DCS Network
is not designed for DMA burst transfers.
Modules that transfer smaller data items (8- or 16-bit) must observe the packing rules
in
DTL-D[31:24]
4n+3
item #1 with
address a
item #4 with
address a+3
DTL_D[31:24]
item #4 with
address a+3
item #2 with address a+2
bits 7..0
item #2 with address a+2
bits 15..8
item with address a
bits 7..0
item with address a
bits 31..24
Table
Table
7.
8.
Rev. 1 — 17 March 2006
DTL-D[23:16]
4n+2
DTL_D[23:16]
item #3 with
address a+2
bits 15..8
bits 7..0
bits 15..8
bits 23..16
DCS_D[23:16]
item #2 with
address a+1
item #3 with
address a+2
DTL_D[15:8]
item #2 with
address a+1
item #1 with address a
bits 7..0
item #1 with address a
bits 15..8
bits 23..16
bits 15..8
DTL-D[15:8]
4n+1
DCS_D[15:8]
item #3 with
address a+2
item #2 with
address a+1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 29: Endian Mode
Table
DTL-D[7:0]
4n+0
DTL_D[7:0]
item #1 with
address a
bits 15..8
bits 7..0
bits 31..24
bits 7..0
6. A given byte lane
DCS_D[7:0]
item #4 with
address a+3
item #1 with
address a
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