pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 723

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
register. The device driver writes the number of descriptors and status words (4) in
the RxDescriptorNumber register. The descriptors and status words in the arrays
need not be initialized, yet.
After allocating the descriptors, a fragment buffer must be allocated for each of the
descriptors. Each fragment buffer can be between 0 and 2K bytes. The base address
of the fragment buffer is stored in the Packet field of the descriptors. The number of
bytes in the fragment buffer is stored in the Size field of the descriptor Control word.
The Interrupt field in the Control word of the descriptor can be set to generate an
interrupt as soon as the descriptor has been filled by the receive process. In this
example the fragment buffers are 8 bytes, so the value of the Size field in the Control
word of the descriptor is set to 7. Note that in this example the fragment buffers are
actually a continuous memory space; even when a packet is distributed over multiple
fragments, most of the time it will be in a linear, continuous memory space; only when
the descriptors wrap at the end of the descriptor array will the packet not be in a
continuous memory space.
The device driver should enable the receive process by writing a 1 to the RxEnable bit
of the Command register after which the MAC must be enabled by writing a 1 to the
RECEIVE_ENABLE bit of the MAC1 configuration register. The LAN100 will now start
receiving Ethernet packets. To reduce the processor interrupt load, some interrupts
can be disabled by setting the relevant bits in the IntEnable register.
After the Rx DMA manager is enabled, it will start reading descriptors from memory.
In this example, the number of descriptors is 4. Initially the RxProduceIndex and
RxConsumeIndex are 0. Since the descriptor array is considered full if
RxProduceIndex == RxConsumeIndex – 1, the Rx DMA manager can only read
(RxConsumeIndex – RxProduceIndex – 1) = 3 descriptors (note the index wrapping).
The Rx DMA manager reads the descriptors from memory; the start address will be
0xFEEDBDEC (RxDescriptor) and the block size will be 3 descriptors * 2 words per
descriptor –1 = 5 (because the block size is –1 encoded).
While descriptor read commands the Rx DMA manager also sets itself up to write the
transmission status. The status write command address will be taken from the
RxStatus register; the block size value will be 3 status words * 1 double word –1 = 2
(because block size is –1 encoded).
After enabling the receive function in the LAN100, it will start receiving data from the
MII Interface starting at the next packet. That is, if the receive function is enabled
while the MII Interface is in the middle of a packet, that packet will be discarded and
reception will start with the next packet. The LAN100 will strip the preamble and
start-of-frame delimiter from the packet. If the packet passes the receive filtering, the
Rx DMA manager will start writing the packet to the first fragment buffer.
For example, if the incomming packet is 19 bytes, then it will be distributed over three
fragment buffers. After writing the initial 8 bytes in the first fragment buffer, the status
for the first fragment buffer will be written and the Rx DMA will continue filling the
second fragment buffer. Since this is a multi-fragment receive, the status word of the
first fragment will have a 0 for the Last bit in the StatusInfo word; the EntryLevel field
will be set to 7 (for a value of 8, because of –1 encoding). After writing the 8 bytes in
the second fragment, the Rx DMA will continue writing the third fragment. The status
of the second fragment will be like the status of the first fragment: Last = 0, EntryLevel
= 7. After writing the three bytes in the third fragment buffer, the end of the packet has
Rev. 1 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
23-50