pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 131

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 8: Global Registers
PNX17XX_SER_1
Preliminary data sheet
7
6
Bit
Symbol
VDO_MODE
VDO_MODE
…Continued
Acces
s
R/W
R/W
Value
0
0
Rev. 1 — 17 March 2006
Description
If set to ‘1’ and VDO_MODE[2:0] set to 0, then in addition to the
QVCP to the TFT interface mapping the FGPO 8-bit LSBs map as
follows:
VDO_D34
FGPO_BUF_SYNC -> (clk_fgpo FF) -> fgpo_data[6]
FGPO_REC_SYNC -> (clk_fgpo FF) -> fgpo_data[5]
VDO_D33
VDO_D32
VDO_D[2:0]
This mode allows to have, for example, a ITU-656 video stream
coming out of FGPO while the QVCP drives a 24-bit TFT LCD
panel.
If set to ‘1’ and VDO_MODE[2:0] set to 4, then in addition to the
regular QVCP mapping the FGPO 8-bit LSBs map as follows:
VDO_D34
FGPO_BUF_SYNC -> (clk_fgpo FF) -> fgpo_data[6]
FGPO_REC_SYNC -> (clk_fgpo FF) -> fgpo_data[5]
VDO_D[4:0]
This mode allows to have, for example, a ITU-656 video stream
coming out of FGPO while the QVCP drives a 24-bit RGB panel or a
dual clock edge 12-bit HD interface (if VDO_MODE[6] is set to ‘1’).
‘0’: No action
‘1’: When VDO_MODE[2:0] = 100, i.e. digital 24-bit YUV or RGB
video:
QVCP_DATA[15:12,9:2]
QVCP_DATA[29:22,19:16]
i.e. G[3:0], B[7:0]
i.e. R[7:0], G[7:4]
i.e. U[3:0], V[7:0]
i.e. Y[7:0], U[7:4]
All the other VDO pins are mapped as described below for
VDO_MODE[2:0] = 100.
This mode is typically used to interface with Video Encoders like the
Philips SAA7104 that require the video data to be presented on both
edges of the pixel clock. This mode allows to transfer the 24-bit data
over a 12-bit interface, VDO_D[16:5].
Note: The YUV mode does not match the SAA7104 expected
inputs. Use the RGB mode instead.
Note: This mode requires a 50/50 duty cycle clock. This can be
achieved by programming the QVCP PLL at twice the speed and
divide it by 2 by setting the P divider to 1, or use a times 4 or 8 as
described in
Section PLL Settings page
-> (clk_fgpo FF) -> fgpo_data[7]
-> (clk_fgpo FF) -> fgpo_data[4]
-> (clk_fgpo FF) -> fgpo_data[3]
-> (clk_fgpo FF) -> fgpo_data[2:0]
-> (clk_fgpo FF) -> fgpo_data[7]
-> (clk_fgpo FF) -> fgpo_data[4:0]
Chapter 3: System On Chip Resources
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=0
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=1
-> VDO_D[16:5] when VDO_CLK1=0
-> VDO_D[16:5] when VDO_CLK1=0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
5-9.
3-22