pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 533

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 1: Audio-In I2S Related Ports
PNX17XX_SER_1
Preliminary data sheet
Signal
AI_OSCLK
AI_SCK
AI_SD[3:0]
AI_WS
Type
Input
In/out
Input
In/out
2.1 Chip Level External Interface
The Audio In chip level I2S related external interface has seven pins AI_OSCLK,
AI_SCK, AI_WS and AI_SD[3:0]. These pins may be also referenced as OSCLK,
SCK, WS and SD[3:0].
The AI_OSCLK is a precise, programmable clock output intended to serve as the
master system clock for the external A/D subsystem. The AI_OSCLK is generated
from the Clock module which is outside the Audio In block. Although conceptually the
oversampling clock is an output at the chip level, at the Audio In block level, this is an
input. Six other pins constitute a flexible serial input interface IP.
Using the Audio In MMIO registers, these pins can be configured to operate in a
variety of serial interface framing modes, including but not limited to the following:
Description
Oversampling Clock. This can be programmed to emit any frequency up to 40 MHz with a
resolution of better than 0.3 Hz. It is intended for use as the 256 f
clock by external A/D subsystem.It is also used by the Audio in block to generate AI_SCK
when it is in master mode. This is generated from the clock block, outside the Audio In
module. It is an output from the chip, but also an input to the Audio Input block.
When Audio In is programmed as the serial-interface timing slave (power-up default), SCK is
an input. SCK receives the serial bit clock from the external A/D subsystem. This clock is
treated as fully asynchronous to the main chip level clock. When Audio In is programmed as
the serial-interface timing master, SCK is an output. SCK drives the serial clock for the
external A/D subsystem. The frequency is a programmable integral divide of the OSCLK
frequency.
SCK is limited to 30 MHz. The sample rate of valid samples embedded within the serial
stream is limited to 100 kHz.
Serial Data from external A/D subsystem. Data on these pins are sampled on positive or
negative edges of SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL register.
When Audio In is programmed as the serial-interface timing slave (power-up default), WS
acts as an input. WS is sampled on the same edge as selected for SD. When Audio In is
programmed as the serial-interface timing master, WS acts as an output. It is asserted on
the
opposite edge of the SD sampling edge.
WS is the word-select or frame-synchronization signal from/to the external A/D subsystem.
•
•
•
AI_SCK = Audio In Serial Clock
AI_WS = Audio In Word Select
AI_SD[3:0] = Audio In Serial Data
Standard stereo I
frame). (For further details on I
5 1996, in the Multimedia ICs Data Handbook IC22 by Philips Semiconductors,
1998.)
LSB first with 1- to 32-bit data per channel
Complex serial frames of up to 512 bits/frame with “valid sample” qualifier bit
0 = Left Channel
1 = Right Channel
Rev. 1 — 17 March 2006
2
S (MSB first, 1-bit delay from WS, left and right data in a
2
S, refer to the “I
2
S Bus Specification” dated June
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 16: Audio Input
s
or 384 f
s
oversampling
16-3