pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 434
pnx1700
Manufacturer Part Number
pnx1700
Description
Connected Media Processor
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700.pdf
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Philips Semiconductors
Volume 1 of 1
Table 1: VIP Submodule Descriptions
PNX17XX_SER_1
Preliminary data sheet
Submodule
Test Pattern
Video Timing
Control
Video Extract
Pre-Dither and Post-
Dither
Up Sample
Horizontal Poly
Phase FIR
Down Sample
AUX Data Extract
3 Channel Write
DMA Control
Figure 2:
VIP Module Interface
2.2.1 Data Routing and Video Modes
Brief Description of Functionality
An internal generator that produces 4:2:2 NTSC/PAL video streams
This submodule receives incoming data samples from either the Test Pattern Generator or the Digital
Video Port.
A tally of the sample is maintained when it conforms to the ITU-R 656 or ITU-R 1364.
Video and Aux samples are forwarded to Video Extract and Aux Data Extract respectively.
Video input pipe windower. This submodule:
receives video samples from Video Port Input module.
captures desired samples in a programmable size rectangular area (window).
forwards captured samples to the Pre-Dither unit.
Video input pipe AUX windower. This submodule:
receives aux samples from Video Port Input module.
captures desired samples in a programmable captured window and/or within a buffer space.
captures ANC packet with matching DID
captures all valid input samples
forwards the captured samples to Pixel Packer.
• There are two identical Dither units: Pre-Dither and Post-Dither, capable of 10->9, 10->8 and 9->8
• 4:2:2 to 4:4:4 Interpolation FIR Filter for chroma upsampling
• Horizontal scaler pipeline
• 4:4:4 to 4:2:2 Decimation FIR Filter for chroma down sampling
• An interface to the memory agent
2.2 Chip I/O and Connections
dithering/rounding of the video data only. The recommended mode is to have rounding for 10->9
and dithering for 9->8
8-bit video samples are received from Post-Dither.
A brief description of each of the submodules is given in
Figure 2
Chip
the PNX17xx Series I/O pins.
The VIP can be operated in three different modes.
Resources,
sketches the input pins of the VIP module. Refer to
Section 7. on page 3-16
Rev. 1 — 17 March 2006
dv_d_data[9:0] (Channel B)
hrefhd
vrefhd
frefhd
dv_data[9:0] (Channel A)
VIP
for the mapping of the VIP I/O signal with
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table
PNX17xx Series
Chapter 3 System On
1.
12-3
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