pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 823

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
3. Register Descriptions
PNX17XX_SER_1
Preliminary data sheet
2.4 Endian Mode
3.1 Register Summary
that most recently performed a transaction. The initiator with a default grant can
access a target one clock cycle faster than an initiator without the default grant.
Assigning the default grant to the initiator that most recently used the “bus” is
expected to yield the highest performance, since one initiator is likely to execute
several transactions at once.
To achieve the round robin feature with a dynamic default grant, the arbiter uses an
internal priority comparator. The comparator selects an initiator to grant by comparing
the “priorities” of each device. The priority value consists of three bits. The most
significant bit is high when there is a pending request from that initiator. The second
most significant bit is generated by “last_grant”, which will be high for the most
recently granted initiator only if that initiator does not have a pending request , and low
for all other initiators. The third bit is a “uniform scheduling” value. This will be set to
one for all bit locations higher than the last granted initiator and zero for all lower
ones. The priority block will pick the highest value (3-bit) input. In the case of a tie, the
lower numbered port will win.
All DCS network ports use 32-bit data paths and the data values are viewed as 32-bit
quantities. Even when an 8 or 16-bit read or write is performed, the transfer is
considered to be a portion of a larger 32-bit quantity. The data transfers are never
viewed as packed 8 or 16-bit values.
Table 1
Table 1:
Remark: The BC_INT_EN register is R/W, however newly written software drivers
should consider BC_INT_EN as read only and should use the BC_INT_CLR_ENABLE
and BC_INT_SET_ENABLE registers to update the value of BC_INT_EN.
Offset
0x10 3000
0x10 300C
0x10 3010
0x10 30D8
0x10 30DC
0x10 3FE0
0x10 3FE4
0x10 3FE8
0x10 3FEC
0x10 3FFC
summarizes the control and status registers visible inside the DCS Controller.
DCS Controller_TriMedia
Symbol
BC_CTRL
BC_ADDR
BC_STAT
BC_INT_CLR_ENABLE
BC_INT_SET_ENABLE
BC_INT_STATUS
BC_INT_EN
BC_INT_CLR
BC_INT_SET
BC_MOD_ID
Rev. 1 — 17 March 2006
Configuration Register Summary
Description
Timeout control register
Error and timeout address register
Error and timeout status register
Clear bits in BC_INT_EN
Set bits in BC_INT_EN
Interrupt Status register
Interrupt Enable register
Interrupt Clear register
Interrupt software set register
Module identification and revision information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Chapter 30: DCS Network
30-3