pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 693

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
PNX17XX_SER_1
Preliminary data sheet
Bit
31:16
15:0
Offset 0x07 21FC
The global time-stamp register records the 32-bit running value of the global Time-stamp Clock. Internally, the counter is
used to generate the time-stamp field in the transmit/receive status fields. In the real-time transmit mode, it is used as a
reference for the transmit arbiter.
Offset 0x07 2200
31:14
13
12
11:8
7
6
5
4
3
2
1
0
Offset 0x07 2204
The bits in this register store the cause for a WoL. Status can be cleared by writing the RxFilterWoLClear register.
31:9
8
7
6
5
31:0
Symbol
-
MirrorCounterCurrent
GlobalTimeStamp
-
RxFilterEnWoL
MagicPacketEnWoL
PatternMatchEn
AndOr
-
AcceptPerfectEn
AcceptMulticastHashEn
AcceptUnicastHashEn
AcceptMulticastEn
AcceptBroadcastEn
AcceptUnicastEn
-
MagicPacketWoL
RxFilterWoL
PatternMatchWoL
AcceptPerfectWoL
Global Time-stamp Register (GlobalTimeStamp)
Receive Filter Control Register (RxFilterCtrl)
Receive Filter WoL Status Register (RxFilterWoLStatus)
…Continued
Acces
s
-
RO
RO
-
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
-
RO
RO
RO
RO
Value
Rev. 1 — 17 March 2006
Description
Unused
In full-duplex mode, this register represents the current value of the
datapath’s mirror counter which counts up to the value of the
MirrorCounter bits from the FlowControlCounter register. In
half-duplex mode, the datapath’s mirror counter counts until it
reaches the value of the PauseTimer bits in the FlowControlCounter
register.
Binary (not grey-coded) value of the global Time-stamp Counter.
Unused
When set, the result of the perfect address matching filter, the
imperfect hash filter, and the pattern match filter will generate a WoL
interrupt in case of a match.
When set, the result of the magic packet filter will generate a WoL
interrupt in case of a match.
Each of the four bits enables one of the pattern-matching filter units.
The lowest order bit corresponds to filter unit 0.
The AND/OR relation between the pattern-matching filter and the
accepting group of bits below. If set, the result of the pattern match
filter is ANDed with the ORed results of the accepting group below.
When set to 0, the result of the pattern-matching filter is ORed with
the ORed results of the accepting group below. See
Unused
When set to ‘1’, the packets with an address identical to the station
address are accepted.
When set to ‘1’, multicast packets that pass the imperfect hash filter
are accepted.
When set to ‘1’, unicast packets that pass the imperfect hash filter
are accepted.
When set to ‘1’, all multicast packets are accepted.
When set to ‘1’, all broadcast packets are accepted.
When set to ‘1’, all unicast packets are accepted.
Unused
When set to ‘1’, a magic packet filter caused WoL.
When set to ‘1’, the receive filter caused WoL.
When set to ‘1’, the pattern-matching filter caused WoL.
When set to ‘1’, the perfect address-matching filter caused WoL.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Section
5.2.
23-20