peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 109

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Table 2-16 DSP Data Address Space
Address
0000
0400
4000
C000
E000
F000
F100
F400
F7F0
F800
FE00
1)
2)
2.7.3
The external data and program memories are accessed through a multiplexed data and
program bus. This bus includes a 16-bit address bus (CA) and 16-bit data bus (CD). The
DCU is generating the read and write controls for these memories and controls the input
and output pads.
The external bus is usually used for fetching program instructions, therefore it’s defined
with program priority. It means that every external bus sequence starts with a program
fetch (always zero wait states). If there is need for data access, the external bus
sequence is extended to a minimum of 4 cycles in the following way:
• cycle 1 - Program fetch
• cycle 2 - IDLE1 cycle
• cycle 3 - Data access (can be extended up to 8 cycles = 7 wait states)
• cycle 4 - IDLE2 cycle
If instead of a program fetch there is a program write, the OAK receives three wait states
(see program write diagram). The program write is always performed by the OAK using
the MOVD instruction (it ensures that a program write will never be in parallel to a data
access). The MOVD instruction is a four cycle instruction therefore, due to the extra wait
Semiconductor Group
For accessing the external data memory 0 to 7 waitstates can be selected. This leads to three to ten more DSP
cycles for external data read and write.
If the DSP tries to write to the circular buffer in the same time that the PEDIU uses it, the PEDIU has higher
priority. In this case, up to four more DSP cycles will be added to the access.
The User should dedicate 0.5 KWord of Program RAM for the monitor (the routine used by the emulator).
H
H
H
H
H
H
H
H
H
H
H
-03FF
-3FFF
-BFFF
-F0FF
-F3FF
- F7EE
-FDFF
-EFFF
-F7FF
-DFFF
-FFFF
Control of External Memories / Registers
H
H
H
H
H
H
H
H
H
H
H
Size
1 KW
15 KW
32 KW
8 KW
4 KW
256 W
0.75 KW
1 KW-16
16 W
1.5 KW
0.5 KW
Number
of Wait
States
0
−
0-7
0
−
0
−
0-7
1
−
0
2)
Number
of DSP
Cycles
1
−
4-11
1
−
1
−
4-11
2
−
1
2)
2-63
1)
1)
Description
Internal XRAM
unused
External data memory
OAK memory mapped registers
unused
Circular RAM buffer
unused
Emulation mail box (on CDI)
OCEM Registers
unused
Internal YRAM
Functional Block Description
PEB 20560
2003-08