peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 319

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
ITF
Note: ITF has to be set 0 if clock mode 3 is used.
CM2
CM1…0
5.1.1.6.9
Access: read/write
Reset value: 00
SOC1,
SOC0
bit 7
SOC1
Due to the delay of TSCA / TSCB in this mode (see description of bits SOC(0:1)
in register CCR2 (chapter 5.1.1.5.9) these signals cannot directly be used to
enable this buffer.
Channel Configuration Register 2 (CCR2)
Inter frame Time Fill.
Determines the “no data to send” state of the transmit data pin (TxDA/B).
0…continuous IDLE-sequences are output (‘11111111’ bit pattern).
1…continuous FLAG-sequences are output (‘01111110’ bit pattern). In a
Clock rate.
0…single rate data clock
1…double rate data clock
Clock Mode.
Determines the mode in which the data clock is forwarded toward the
receiver/transmitter.
00…clock mode 0: external data clock, permanently enabled.
01…clock mode 1: external data clock, gated by an enable strobe
10…clock mode 2: external data clock, programmable time-slot
11…not allowed
The function of the TSCA/B-pin can be defined programming SOC1,SOC0.
• Bus configuration:
SOC0
00…the TSCA/B output is activated only during the transmission of a
10…the TSCA/B-output is always high (disabled).
In a bus configuration (CCR1:SC0 = 1) ITF is implicitly set to ‘0’
(continuous ‘1’s are transmitted).
bus configuration (CCR1:SC0 = 1) ITF is implicitly set to ‘0’ (continuous
‘1’s are transmitted).
H
frame delayed by one clock period. When transmission was
stopped due to a collision TSCA/B remains inactive.
XCS0
forwarded via pin HFS.
assignment, frame synchronization pulse forwarded via
pin HFS.
RCS0
5-76
TXDE
RDS
Description of Registers
RIE
PEB 20560
bit 0
2003-08
0