peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 178

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Interrupt Vector (INT_VEC)
This is the vector which is being read during interrupt acknowledge cycle.
bit
INT_VEC
The 8-bit vector contains a 4-bit programmable interrupt address base, which can be
programmed via IDOC, and a 4-bit interrupt source identifier (see Table 2-28).
2.13.4
The DOC Interrupt Controller supports two cascading schemes which can be selected
by programming the IPC register.
Interrupt Port Configuration Register (IPC)
Reset Value: 00
µP interface mode: read/write
Address: 301
bit
IPC
Note: Bits 7…6 are unused and are read as ‘0’.
MODE
SLA1…0
CASM
Interrupt Cascading
7
7
H
Interrupt Handling Mode
0…Intel scheme
1…Motorola scheme
Slave Address
Used only in Slave Cascading Mode (refer to CASM).
Cascading Mode
0…Slave Cascading Mode
Pins IE0, IE1 are used as inputs. Interrupt acknowledge is accepted if an
interrupt signal has been generated and the values on pins IE1…0
correspond to the programmed values in SLA1…0 (Slave Address).
1…Daisy Chaining Mode
Pin IE0, as Interrupt Enable Output, and pin IE1, as Interrupt Enable input,
are used for building a Daisy Chain. Interrupt acknowledge is accepted if
an interrupt signal has been generated and Interrupt Enable Input, IE1, is
active “high” during a subsequent IACK cycle(s). If pin INT goes active,
Interrupt Enable Output, IE0, is immediately set to “low”.
0
H
DOC Interrupt Address Base
0
MODE
2-132
4
SLA1
3
SLA0
Functional Block Description
Source Identifier
CASM
IC1
PEB 20560
0
0
2003-08
IC0