peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 154

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.8.3.2
The PEDIU should synchronize FSC DCL and input data streams (down-streams) to the
DSP 2-phase system clock. The DSP clock rate can be 20 MHz, 30 MHz, or 40 MHz:
• When working with DCL rate of 4.096 MHz, the PEDIU will work correctly with any of
• When working with DCL rate of 8.192 MHz, the DSP rate is restricted to 40 MHz.
2.8.4
The PEDIU address space includes 2 address sub-spaces:
• The PEDIU-RAM (circular-buffer) address space
• The PEDIU register address space.
The PEDIU distinguishes between accesses to these two sub-spaces by 4 signals,
which come from the DCL:
• Read and write signals to the RAM space
• Read and write signals to the register space
Accesses of DSP to the register space will be done immediately without any wait states.
During DSP accesses to the RAM address space, some wait states might be necessary,
when the PEDIU DMA accesses the RAM at the same time.
The PEDIU-RAM address-space in the DSP address space is between the addresses:
0xF000 - 0xF3FF. The value in the 8 lsbs define the shift in the PEDIU RAM.
The PEDIU register space in the DSP address space is between the addresses:
0xC100 - 0xC10F. Table 2-26 specifies the use of each address in this space.
Table 2-26 PEDIU Registers Addresses in the DSP Address Space
Address
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C10A
these DSP rates.
H
H
H
H
H
H
H
H
H
H
H
Restrictions on PEDIU Clock Rates
PEDIU Address Space
Use
read and write UCR
read and write USR
set UISBPER
reset UISBPER
read UISBPER
read UOSBPER
set UOSBPER
reset UOSBPER
set UTSR
reset UTSR
read UTSR
2-108
Functional Block Description
PEB 20560
2003-08