peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 188

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Table 2-33 Register Reset Values (cont’d)
Register/Signal
INTR (THRE)
INTR (Modem status changes)
OUT2
RTS
DTR
OUT1
RCVR FIFO
XMIT FIFO
1)
2)
UART Address 2-0
Address signals connected to these 3 inputs select a UART register for the µP to read
from or write to during data transfer. A table of registers and their addresses is shown
below. Note that the state of the divisor latch access bit (DLAB), which is the most
significant bit of the line control register, affects the selection of certain UART registers.
The DLAB must be set high by the system software to access the baud rate generator
divisor latches
.
Table 2-34 UART Registers and Addresses
DLAB
0
0
X
X
X
X
X
X
X
1
1
Boldface bits are permanently low.
Bits 7-4 are driven by the input signals.
A2
0
0
0
0
0
1
1
1
1
0
0
A1
0
0
1
1
1
0
0
1
1
0
0
A0
0
1
0
0
1
0
1
0
1
0
1
Reset Control
Read IlR/write THR/MR
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
MR/RFR • FEWO/∆FEWO
MR/T FR • FEWO/∆FEWO
2-142
Register
Receiver buffer (read), Transmitter holding
register (write)
Interrupt enable
Interrupt identification (read)
FIFO control (write)
Line control
Modem control
Line status
Modem status
Scratch
Divisor latch (least significant byte)
Divisor latch (most significant byte)
Functional Block Description
Reset State
Low
Low
High
High
High
High
All bits low
All bits low
PEB 20560
2003-08