peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 272

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

5.1.1.4.4
Access: read/write
Reset value: 00
OFU9…2
5.1.1.4.5
Access: read/write
Reset value: 00
DRCS
OFD1…0
DRE
ADSRO
Note: If both DRCS and ADSRO are set to logical 1, the PCM-output data are delayed
OFU1…0
Semiconductor Group
bit 7
bit 7
DRCS
OFU9
by two PDC-clock cycles.
PCM-Offset Upstream Register (POFU)
PCM-Clock Shift Register; within the ELIC (PCSR)
Offset Upstream bit 9…2.
These bits together with PCSR:OFU1…0 determine the offset of the
PCM-frame in upstream direction. The following formulas apply for
calculating the required register value. BNU is the bit number in upstream
direction marked by the rising internal PFS-edge.
PCM-mode 0:
PCM-mode 1, 3: OFU9…1 = mod
PCM-mode 2:
Double Rate Clock Shift.
0…the PCM-input and output data are not delayed
1…the PCM-input and output data are delayed by one PDC-clock cycle
Offset Downstream bits 1…0, see POFD-register.
Downstream Rising Edge.
0…the PCM-data is sampled with the falling edge of PDC
1…the PCM-data is sampled with the rising edge of PDC
Add Shift Register on Output.
0…the PCM-output data are not delayed
1…the PCM-output data are delayed by one PDC-clock cycle
Offset Upstream bits 1…0, see POFU-register.
OFU8
OFD1
H
H
OFU7
OFD0
OFU9…2 = mode
PCSR:OFU1…00 = 0
PCSR:OFU0 = 0
OFU9…0 = mod
OFU6
DRE
5-29
ADSRO
OFU5
BPF
BPF
BPF
(BNU + 47)
(BNU + 95)
(BNU + 23)
OFU4
OFU1
Description of Registers
OFU3
OFU0
PEB 20560
bit 0
bit 0
OFU2
URE
2003-08