peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 317

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
5.1.1.6.7
Access: read/write
Reset value: 00
MDS1…0 Mode Select.
ADM
Note: In extended transparent mode 0 and 1 the bit MODE:RAC must be reset to enable
CFT
RAC
TLP
bit 7
MDS1
fully transparent reception.
Mode Register (MODE)
MDS0
The operating mode of the HDLC-controller is selected.
00…auto-mode
01…non-auto-mode
11…extended transparent mode
Address Mode.
The meaning of this bit varies depending on the selected operating mode:
• Auto-mode / non-auto mode
• Transparent mode
• Extended transparent mode
Continuous Frame Transmission.
1…when CFT is set the XPR-interrupt is generated immediately after the
0…otherwise the XPR-interrupt is delayed until the transmission is
Receiver Active.
Via RAC the HDLC-receiver can be activated/deactivated.
0…HDLC-receiver inactive
1…HDLC-receiver active
In extended transparent mode 0 and 1 RAC must be reset (HDLC-receiver
disabled) to enable fully transparent reception.
Test Loop.
When set input and output of the HDLC-channel are internally connected.
(transmitter channel A - receiver channel A
Defines the length of the HDLC-address field.
0…8-bit address field,
1…16-bit address field.
0… no address recognition: transparent mode 0 (D-channel arbiter)
1… high byte address recognition: transparent mode 1
0… receive data in RAL1: extended transparent mode 0
1… receive data in RFIFO and RAL1: extended transparent mode 1
H
CPU accessible part of XFIFO is copied into the transmitter section.
completed (D-channel arbiter).
ADM
CFT
5-74
RAC
0
Description of Registers
0
PEB 20560
bit 0
TLP
2003-08