peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 301

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
XPR
Each interrupt source can be selectively masked by setting the respective bit in the
MASK_A/B-register (bit position corresponding to the ISTA_A/B-register). Masked
interrupts are internally stored but not indicated when reading ISTA_A/B and also not
flagged into the top level ISTA. After releasing the respective MASK_A/B-bit they will be
indicated again in ISTA_A/B and in the top level ISTA.
When writing register MASK_A/B while ISTA_A/B indicates a non masked interrupt the
INT-pin is temporarily set into the inactive state. In this case the interrupt remains
indicated in the ISTA_A/B until these registers are read.
5.1.1.5.5
Access: read
Reset value: 00
XMR
XDU/EXE Transmission Data Underrun/Extended transmission End.
Note: It is not possible to transmit frames when a XMR- or XDU-interrupt is indicated.
EHC
bit 7
XMR
Extended Interrupt Register (EXIR_A/B)
enables(0)/disables(1) the Transmit Pool Ready interrupt.
XDU/EXE
Transmit Message Repeat.
The transmission of a frame has to be repeated because:
– A frame consisting of more then 32 bytes is polled a second time in
– Collision has occurred after sending the 32nd data byte of a message in
– CTS (transmission enable) has been withdrawn after sending the 32nd
The actual frame has been aborted with IDLE, because the XFIFO holds no
further data, but the frame is not yet complete according to registers
XBCH/XBCL.
In extended transparent mode, this bit indicates the transmission end
condition.
Extended HDLC-frame.
The SACCO has received a frame in auto-mode which is neither a RR- nor
an I-frame. The control byte is stored temporarily in the RHCR-register but
not in the RFIFO.
auto-mode.
a bus configuration.
data byte of a message in point-to-point configuration.
H
EHC
RFO
5-58
0
RFS
Description of Registers
0
PEB 20560
bit 0
2003-08
0