peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 48

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.1.2.2
After power-up the ELIC is latched into the “Resetting” state. Therefor an integrated
power-up reset generator is provided. Additionally an external reset input (DRESET) and
an reset indication output (RESIN) are available. A microprocessor access is not
possible in the “Resetting” state. The ELIC is released from the power-up “Resetting”
state when provided with PFS- and PDC-signals for 8 PFS-periods.
The ELIC can also be reset by applying a DRESET-pulse for at least 4 PDC-periods.
Note that such an external DRESET has priority over a power-on reset. It is thus possible
to kill the 8-frame reset duration after power-up. For correct DRESET a main clock must
be applied to CLK61.
During reset all ELIC-outputs with the exception of RESIN and TDO + DRQRA/B +
DRQTA/B + SACCO are in the state high impedance. The tri-state control signals of the
EPIC-1 PCM-interface (TSC[3:0]) TSCA/B are not tri-stated during a chip reset. Instead
they are high during reset, thus containing the correct tri-state information for external
drivers.
RESIN is set upon power up, DRESET and the expiring of the watchdog timer. It may be
used as a system reset. RESIN is activated for 8 PFS-periods (assuming an active
PDC-input) or it has the same pulse width as DRESET. DRESET has priority over
internal generated resets with respect to the RESIN pulse width. The activation of
DRESET causes an immediate activation of RESIN. Upon the deactivation of DRESET
however, RESIN is deactivated only with the next rising PDC-edge. A PFS-frequency of
8-kHz results in a RESIN-period of 1 ms.
When setting bit VNSR:SWRX RESIN is also activated but the ELIC itself is not reset.
This feature supports a proper reset procedure for devices which require dedicated
clocking during reset. The sequence required is as follows:
1. Initialize EPIC-1 for a timer interrupt
2. Set bit VNSR:SWRX to ‘1’, RESIN is activated
3. When the timer interrupt occurs, RESIN is deactivated
4. Set bit VNSR:SWRX to ‘0’
5. Read ISTA_E, in order to deactivate timer interrupt
Table 2-2 Reset Activities
Power up
Watchdog timer under flow
External reset (DRESET)
Setting of bit SWRX
Reset Logic
Internal ELIC
Reset
X
–
X
–
2-2
RESIN
Activation
X
X
X
X
Functional Block Description
RESIN Pulse
Width
8 PFS
8 PFS
DRESET
Programmable
PEB 20560
2003-08