peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 151

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Table 2-25 describes which time-slot quadruplet is controlled by each UOSBPER bit in
each PEDIU work mode.
The setting and resetting methods of UTSR are exactly like those of UISBPER and
UOSBER; only the addresses are different. Every ‘1’ in the written word indicates a bit
that should be set or reset, depending on the address, and every ‘0’ indicates a bit that
should not be changed.
The addresses for setting and resetting of UTSR:
0xC108: Set UTSR.
0xC109: Resetet UTSR.
The address for reading UTSR is 0xC10A.
UTSR
For each bit in UTSR:
‘0’
‘1’
After reset all bits of UTSR are ‘0’.
Table 2-25 Specification of the Time-Slot Quadruplet Controlled by Each Bit in
UTSR Bit
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
Semiconductor Group
bit
The PEDIU does not drive the related DU-line (ELIC0-DU0 or ELIC1-DU1) during
the related sequential quadruplet of time-slots.
The PEDIU drives the related DU-line (ELIC0-DU0 or ELIC1-DU1) during the
related sequential quadruplet of time-slots. The bit sequence in the read word will
be the same as in UTSR.
15
ts15 ts14 ts13 ts12 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0
UOSBPER, in the Different Work Modes of the PEDIU
Output Stream
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT1
OUT1
Mode 0/1/2
Time-Slots
12-15
16-19
20-23
24-27
28-31
0-3
4-7
0-3
4-7
8-11
2-105
Output Stream
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
Functional Block Description
Mode 3/4
Time-Slots
0-3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
32-35
36-39
PEB 20560
2003-08
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