peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 237

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

PEB 20560
DSP Core OAK
The CU has a 16 by 16 bit multiplier (which performs signed by signed, signed by
unsigned or unsigned by unsigned multiplications) supporting single and double
precision multiplication. The CU has also a 36-bit ALU, and two 36-bit accumulators with
access to the two additional accumulators of the BMU.
The BMU consists of a full 36-bit barrel shifter, a bit-field operations (BFO) unit including
a special hardware for exponent calculation, and two 36-bit accumulators with access to
the two accumulators of the CU. Context switching (swapping) between the two sets of
accumulators is supported.
The DAAU, the PCU, the data and program memory organization, and buses structure
are basically similar to those of SPC.
Powerful zero-overhead looping, enables four levels of block-repeat (BKREP), in
addition to an interruptable single word Repeat. The pipeline structure has been
improved to achieve minimal cycle time. An index-based addressing capability was
added. Shadow registers for parts of the status registers and alternative bank of registers
for four of the DAAU registers were added to improve interrupt handling and subroutine
nesting. Option for automatic context switching during interrupts is also included.
The hardware stack of SPC is substituted with a more flexible software stack residing in
the data memory space. This improvement, as well as the indexed-based addressing
capability and the additional accumulators, will also support a C-compiler
implementation for OAK.
An additional maskable interrupt has been added to the core and a NMI interrupt (used
in SPC for emulation by the name BPI) was released to the user as a non-maskable
interrupt. For emulation support a Breakpoint interrupt (BI) was added, sharing the same
interrupt vector of TRAP.
The core is designed to interface with external memories and peripherals having
different speeds, using a wait-state mechanism. It supports DMA mode and hold mode
operation. It also has support for an automatic boot procedure, and it has support for
on-chip emulation module, residing off-core.
Semiconductor Group
4-2
2003-08