peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 335

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
TD7…0
5.1.2.3
Access: read
Reset value: 00
RME
RPF
XPR
5.1.2.4
Access: write
Reset value: 00
RME
RPF
XPR
Each interrupt source can be selectively masked by setting the respective bit in the
MASK_A/B-register (bit position corresponding to the ISTA_A/B-register). Masked
interrupts are internally stored but not indicated when reading ISTA_A/B and also not
flagged into the top level ISTA. After releasing the respective MASK_A/B-bit they will be
indicated again in ISTA_A/B and in the top level ISTA.
bit 7
bit 7
RME
RME
Interrupt Status Register (ISTA_A/B)
Mask Register (MASK_A/B)
Transmit Data 7…0, data byte to be transmitted on the serial interface.
Interrupt controlled data transfer.
Up to 32 bytes of transmit data can be written to the XFIFO following an
XPR-interrupt.
Receive Message End.
A message of up to 32 bytes or the last part of a message greater then
32 bytes has been received and is now available in the RFIFO. The
message is complete! The actual message length can be determined by
reading the registers RBCL, RBCH. RME is not generated when an
extended HDLC- frame is recognized in auto-mode (EHC interrupt).
Receive Pool Full.
A data block of 32 bytes is stored in the RFIFO. The message is not yet
completed!
Transmit Pool Ready.
A data block of up to 32 bytes can be written to the XFIFO.
enables(0)/disables(1) the Receive Message End interrupt.
enables(0)/disables(1) the Receive Pool Full interrupts.
enables(0)/disables(1) the Transmit Pool Ready interrupt.
RPF
RPF
H
H
(all interrupts enabled)
0
0
XPR
XPR
5-92
0
0
0
0
Description of Registers
0
0
PEB 20560
bit 0
bit 0
2003-08
0
0