hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 101

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
11) MIN (t
12) The t
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
14) 0 ≤ T
15) 85 < T
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The t
18) x4 & x8
19) x16
20) The maximum limit for the t
21) Minimum t
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
Table 54
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQ and DM input setup time (single-ended strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Data Sheet
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
this value can be greater than the minimum specification limits for t
no longer driving (t
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
between 85 °C and 95 °C.
but system performance (bus turnaround) degrades accordingly.
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing t
mode” (MR, A12 =”1”) a slow power-down exit timing t
HZ
CASE
RRD
CL
CASE
, t
, t
RPST
timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
CH
≤ 85 °C
Timing Parameter by Speed Grade - DDR2-400
WTR
≤ 95 °C
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
and t
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
HZ
LZ
, t
, t
RPRE
RPST
), or begins driving (t
WPST
parameters are referenced to a specific voltage level, which specify when the device output is
parameter is not a device limit. The device operates with a greater value for this parameter,
LZ
, t
RPRE
XARDS
). t
102
HZ
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
and t
has to be satisfied.
(base)
(base)
(base)
(base)
(base)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
LZ
CL
transitions occur in the same access time windows as
and t
XARD
DDR2-400
Min.
–600
2
0.45
3
0.45
WR +
t
275
25
0.35
–500
0.35
—
– 0.25
150
25
0.2
0.2
MIN. (
—
475
CH
IS
).
+
can be used. In “low active power-down
t
CK
t
t
CL,
RP
+
t
t
IH
CH
512-Mbit DDR2 SDRAM
)
Max.
+600
—
0.55
—
0.55
—
––
––
––
—
+500
—
350
+ 0.25
—
—
—
—
t
—
AC.MAX
Electrical Characteristics
09112003-SDM9-IQ3P
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ps
ps
Rev. 1.6, 2005-08
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Note
1)2)3)4)5)6)
7)
8)
9)
10)
11)
9)
9)
12)
13)
9)