hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 30

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 8
Field
BT
BL
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing t
3.6
The Extended Mode Register EMR(1) stores the data
for enabling or disabling the DLL, output driver
strength, additive latency, OCD program, ODT, DQS
and output buffers disable, RQDS and RDQS enable.
The default value of the extended mode register
Table 9
Field
BA2
BA1
BA0
Data Sheet
t
fulfill the minimum requirement for the analogue t
t
CK
CK.MIN
(in ns) and rounding up to the next integer: WR [cycles] ≥ t
.
Bits
3
[2:0]
Bits
16
15
14
Mode Register Definition (BA[2:0] = 000B)
DDR2 SDRAM Extended Mode Register Set (MRS)
Extended Mode Register Definition (BA[2:0] = 001B)
Type
w
w
Type
reg. addr.
1)
1)
Description
Burst Type
0
1
Burst Length
Note: All other bit combinations are illegal.
010
011
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0
Bank Address [1]
0
Bank Address [0]
0
B
B
B
B
B
B
B
BT, Sequential
BT, Interleaved
BL, 4
BL, 8
BA2, Bank Address
BA1, Bank Address
BA0, Bank Address
WR
timing WR
31
EMR(1) is not defined, therefore the extended mode
register must be written after power-up for proper
operation. The extended mode register is written by
asserting low on CS, RAS, CAS, WE, BA1 and high on
BA0, while controlling the state of the address pins
WR
MIN
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
(ns) / t
is determined by t
CK
(ns). The mode register must be programmed to
CK.MAX
512-Mbit DDR2 SDRAM
and WR
Functional Description
09112003-SDM9-IQ3P
MAX
Rev. 1.6, 2005-08
is determined by
WR
(in ns) by