hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 56

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.21
Interruption of a read or write burst is prohibited for
burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. A Read Burst can only be interrupted by another
2. A Write Burst can only be interrupted by another
3. Read burst interrupt must occur exactly two clocks
4. Write burst interrupt must occur exactly two clocks
5. Read or Write burst interruption is allowed to any
Figure 38
CL = 3, AL = 0, RL = 3, BL = 8
Figure 39
CL = 3, AL = 0, WL = 2, BL = 8
Data Sheet
Read command. Read burst interruption by a Write
or Precharge Command is prohibited.
Write command. Write burst interruption by a Read
or Precharge Command is prohibited.
after the previous Read command. Any other Read
burst interrupt timings are prohibited.
after the previous Write command. Any other Read
burst interrupt timings are prohibited.
bank inside the DDR2 SDRAM.
C K , C K
C M D
D Q S ,
D Q S
D Q
C M D
D Q S ,
D Q S
C K , C K
D Q
Burst Interruption
Read Interrupt Timing Example 1
Write Interrupt Timing Example 2
T0
R E A D A
N O P
T0
W R IT E A
T1
T1
N O P
R E A D B
T2
T2
N O P
Din A0
W R IT E B
T3
T3
N O P
Dout A0
Din A1
Dout A1
Din A2
T4
T4
N O P
N O P
Dout A2
Din A3
57
Dout A3 Dout B0
6. Read or Write burst with Auto-Precharge enabled is
7. Read burst interruption is allowed by a Read with
8. Write burst interruption is allowed by a Write with
9. All command timings are referenced to burst length
Din B0
T5
T5
N O P
N O P
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
not allowed to be interrupted.
Auto-Precharge command.
Auto-Precharge command.
set in the mode register. They are not referenced to
the actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual
burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 +
t
un-interrupted burst end and not from the end of the
actual burst end.
WR
Din B1
Dout B1
, where
T6
Din B2
T6
N O P
N O P
Dout B2
Din B3
t
WR
Dout B3 Dout B4
T7
Dout B4
starts with the rising clock after the
T7
N O P
N O P
Din B5
Dout B5
512-Mbit DDR2 SDRAM
RBI
WBI
N O P
Din B6
T8
N O P
Dout B6
T8
Functional Description
09112003-SDM9-IQ3P
Din B7
Dout B7
N O P
Rev. 1.6, 2005-08
N O P