hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 90

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

6
Table 44
Parameter
Operating Current -
One bank Active - Precharge
t
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
bus inputs are floating
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
switching, Data bus inputs are switching
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
stable, Data bus inputs are floating.
Active Power-Down Current
All banks open;
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open;
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
between valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
commands. Address inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
t
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Distributed Refresh Current
t
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Data Sheet
CK
CK
CK
CK
CK
OUT
=
=
=
=
=
= 0 mA, BL = 4,
t
t
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
CK(IDD)
CK(IDD)
,
;
;
, Refresh command every
, Refresh command every
Currents Measurement Specifications and Conditions
I
t
t
t
DD
RC
RAS
RAS
t
t
t
CK
CK
Measurement Conditions
=
CK
=
=
t
=
=
RC(IDD)
=
t
t
RAS.MAX.(IDD)
RAS.MAX(IDD)
t
t
t
CK(IDD)
CK(IDD)
t
CK
.
CK(IDD)
=
,
t
t
RAS
CK(IDD)
, CKE is LOW; Other control and address inputs are stable; Data
, CKE is LOW; Other control and address inputs are stable, Data
;
t
CK
t
RAS
,
=
,
=
t
t
RP
t
,
RP
RAS.MIN(IDD)
=
t
t
CK(IDD)
RC
t
=
=
RAS.MAX(IDD)
t
=
t
RP(IDD)
t
t
RP(IDD)
RFC
REFI
t
.
RC(IDD)
;Other control and address inputs are stable; Data
t
t
CK
CK
=
= 7.8 µs interval, CKE is LOW and CS is HIGH
, CKE is HIGH, CS is HIGH between valid
; CKE is HIGH, CS is HIGH between valid
=
=
; CKE is HIGH, CS is HIGH between valid
t
RFC(IDD)
,
t
t
,
CK(IDD)
CK(IDD)
t
RAS
t
RP
=
=
; Other control and address inputs are
; Other control and address inputs are
interval, CKE is HIGH, CS is HIGH
t
t
RP(IDD)
Currents Measurement Specifications and Conditions
RAS.MIN(IDD)
91
; CKE is HIGH, CS is HIGH
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
,
t
RCD
=
t
RCD(IDD)
I
OUT
(IDD)
(IDD)
= 0 mA.
, AL = 0,
;
;
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Symbol Notes
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
Rev. 1.6, 2005-08
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