hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 99

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

17) x4 & x8 (1k page size)
18) The
19) x16 (2k page size), not on 256Mbit component
20) The maximum limit for the
21) Minimum
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
Table 53
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals) t
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
Data Sheet
but system performance (bus turnaround) degrades accordingly.
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing
mode” (MR, A12 =”1”) a slow power-down exit timing
t
RRD
timing parameter depends on the page size of the DRAM organization. See Chapter 1.5
t
Timing Parameter by Speed Grade - DDR2-533
WTR
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
WPST
parameter is not a device limit. The device operates with a greater value for this parameter,
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
XARDS
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
(base)
(base)
100
(base)
(base)
(base)
(base)
has to be satisfied.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
DDR2–533
Min.
–500
2
0.45
3
0.45
WR + t
t
225
–25
0.35
–450
0.35
—
WL – 0.25
100
–25
0.2
0.2
MIN. (t
—
375
0.6
250
2 ° t
t
2
IS
AC.MIN
t
+ t
XARD
AC.MIN
CK
CL,
RP
+ t
can be used. In “low active power-down
t
IH
CH
)
Max.
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
300
WL + 0.25
—
—
—
—
t
—
—
—
t
t
—
AC.MAX
AC.MAX
AC.MAX
512-Mbit DDR2 SDRAM
Electrical Characteristics
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ps
ps
t
ps
ps
ps
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Note
3)4)5)6)
7)
8)
9)
9)
10)
9)
9)
11)
12)
9)
9)
12)
12)
1)2)