hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 93

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

6.1
For testing the
Table 47
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
Active bank A to Active bank B
command delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh
command period
Auto-Refresh to Active / Auto-Refresh
command period
Average periodic Refresh interval
1) ×4 & ×8 (1 KByte Page Size)
2) ×16 (2 KByte Page Size); not on 256M component
Table 48
Parameter
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh
command period
Active bank A to Active bank B
command delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-
Refresh command period
Average periodic Refresh interval
1) ×4 & ×8 (1KByte Page Size)
2) ×16 (2 KByte Page Size); not on 256M component
Data Sheet
I
I
I
DD
DD
DD
I
DD
Measurement Test Conditions for DDR2–667C and DDR2–667D
Measurement Test Condition for DDR2–533C and DDR2–400B
Test Conditions
parameters, the following timing parameters are used:
t
Symbol
t
t
t
t
t
t
t
t
CL
RAS.MAX(IDD)
CK(IDD)
RCD(IDD)
RC(IDD)
RRD(IDD)
RAS.MIN(IDD)
RP(IDD)
RFC(IDD)
REFI
(IDD)
Symbol
CL
t
t
t
t
t
t
t
t
t
t
t
CK(IDD)
RCD(IDD)
RC(IDD)
RRD(IDD)
RRD(IDD)
RAS.MIN(IDD)
RAS.MAX(IDD)
RP(IDD)
RFC(IDD)
RFC(IDD)
REFI
(IDD)
–3.7
DDR2–533 4–4–4
4
3.75
15
60
7.5
10
45
70000
15
105
7.8
–3
DDR2–667 4–4–4
4
3
12
57
7.5
10
45
70000
12
75
105
7.8
Currents Measurement Specifications and Conditions
94
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
–5
DDR2–400 3–3–3
3
5
15
55
7.5
10
40
70000
15
105
7.8
DDR2–667 5–5–5
15
10
70000
105
7.8
–3S
5
3
60
7.5
45
15
75
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08
ns
ns
Unit
t
ns
ns
ns
ns
ns
ns
ns
µs
CK
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CK
Notes
1)
2)
Notes
1)
2)