hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 69

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Power-Down Entry
Active Power-down mode can be entered after an
Activate command. Precharge Power-down mode can
be entered after a Precharge, Precharge-All or internal
precharge command. It is also allowed to enter power-
mode after an Auto-Refresh command or MRS /
EMRS(1) command when
Active Power-down mode entry is prohibited as long as
a Read Burst is in progress, meaning CKE should be
kept HIGH until the burst operation is finished.
Therefore Active Power-Down mode entry after a Read
or Read with Auto-Precharge command is allowed after
RL + BL/2 is satisfied.
Power-Down Exit
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command can be
Figure 55
Note: Active Power-Down mode exit timing
Example : Active Power-Down Mode Entry and Exit after Read Command : RL = 4 (AL = 1, CL =3), BL = 4
Data Sheet
state in the MR, address bit A12.
Active Power-Down Mode Entry and Exit after an Activate Command
C K E
C K , C K
C M D
t
MRD
A ctivate
T0
is satisfied.
Power-Down
Active
Entry
T1
N O P
tIS
t
XARD
T2
N O P
(“fast exit”) or
70
N O P
Active Power-down mode entry is prohibited as long as
a Write Burst and the internal write recovery is in
progress. In case of a write command, active power-
down mode entry is allowed when WL + BL/2 +
satisfied.
In case of a write command with Auto-Precharge,
Power-down mode entry is allowed after the internal
precharge command has been executed, which is WL
+ BL/2 + WR starting from the write with Auto-
Precharge command. In this case the DDR2 SDRAM
enters the Precharge Power-down mode.
applied with power-down exit latency,
t
latencies are defined in
XARDS
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
Power-Down
t
XARDS
, after CKE goes HIGH. Power-down exit
Active
Tn
Exit
N O P
tIS
(“slow exit”) depends on the programmed
Tn+1
tXARD or
tXARDS *)
N O P
Tn+2
C om m and
Chapter
V alid
512-Mbit DDR2 SDRAM
Act.PD 0
Functional Description
09112003-SDM9-IQ3P
7.2.
Rev. 1.6, 2005-08
t
XP
,
t
XARD
t
WTR
or
is