hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 80

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

5.4
Table 31
Symbol
I
I
1)
2) The values of
3)
Table 32
Symbol
V
V
V
1) SSTL_18 test load for
Table 33
Symbol
—
—
—
S
1) Absolute Specifications (
2)
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
5) Slew Rates according to
6) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
7) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in
8) DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
Data Sheet
OH
OL
OUT
OH
OL
OTR
V
V
to ensure
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
V
has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into
±
additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to
device (13.4 mA × 45 Ohm = 603 mV).
requires DRAM to meet timing, voltage and slew rate specifications on I/O’s.
(
measurement condition for output sink dc current:
for values of
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
±
from AC to AC. This is verified by design and characterization but not subject to production test.
t
Impedance measurement condition for output source dc current:
V
QHS
DDQ
DDQ
DDQ
335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an
0.75 Ohms under nominal conditions.
OUT
specification.
= 1.7 V;
– 280 mV.
= 1.7 V;
–
V
DDQ
V
Parameter
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
Output Buffer Characteristics
SSTL_18 Output DC Current Drive
SSTL_18 Output AC Test Conditions
OCD Default Characteristics
Description
Output Impedance
Pull-up / Pull down mismatch
Output Impedance step size
for OCD calibration
Output Slew Rate
IH.MIN
) /
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
V
I
V
I
OUT
V
OH(dc)
OH
OUT
OUT
. plus a noise margin and
must be less than 23.4 ohms for values of
between 0 V and 280 mV.
= 280 mV.
= 1.42 V. (
and
V
OH
I
T
Chapter 8.2.1
OL(dc)
OPER
and
;
V
are based on the conditions given in
VOL
V
V
OUT
OUT
DD
is different from the referenced load described in
–
= 1.8 V
V
/
DDQ
I
OL
V
IL(ac)
) /
must be less than 21 Ohm for values of
V
IL.MAX
±
I
OH
0.1 V;
to
must be less than 21 Ohm for values of
V
minus a noise margin are delivered to an SSTL_18 receiver. The actual
V
IH(ac)
DDQ
V
DDQ = 1.8 V
with the load specified in
Min.
See
0
0
1.5
= 1.7 V;
81
Chapter 5.5
V
OUT
SSTL_18
13.4
–13.4
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
V
OUT
V
between
DDQ
1)
±
Nominal
—
—
—
= –280 mV;
and
0.1 V), altering OCD from default state no longer
= 1.7 V,
3)
. They are used to test drive current capability
SSTL_18
V
V
0.5 ×
V
TT
TT
DDQ
V
V
+ 0.603
– 0.603
Figure
TT
and
OUT
V
V
V
. The SSTL_18 definition assumes that
OUT
DDQ
Max.
4
1.5
5.0
OUT
Chapter
AC & DC Operating Conditions
= 1420 mV;
V
/
DDQ
between 0 V and 280 mV.
72.
512-Mbit DDR2 SDRAM
I
V
Unit
mA
mA
OL
OUT
– 280 mV. Impedance
must be less than 23.4 Ohms
8.1. The SSTL_18 test load
between
09112003-SDM9-IQ3P
Unit
Ohms
Ohms
Ohms
V / ns
Unit
V
V
V
Rev. 1.6, 2005-08
V
DDQ
V
TT
Notes
1)2)
2)3)
, at the ouput
and
Notes
1)2)
1)2)3)
4)
1)5)6)7)8)
Note
1)
1)
t
DQSQ
and